Steps to read by CPU from ECC RAM within TCRAM Wrapper

Hello Chuck,

Following are the EXCERPTS from another POST in E2E

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/192363.aspx

I ram some sims to figure out the answer.

LDMIA and STMIA will also work. Something else to be cautious about is to disable ECC in the CPU for the time you are reading the ECC from TCRAMW. The TCRAMW does not deliver the correct ECC when you are reading ECC.

The lowest 8b of the r2 are only relevant.

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If you see the above mentioned LINK, you will see RED marked sentence.

But you are saying that ECC on R4 Core need not be disabled.

Abhishek Shankar is telling the opposite.

Can you please help me with some more detailed information?

Thank you.

Regards

Pashan

Hello Chuck,

In the Cortex-R4 r1p3 TRM of ARM, on Page 4-42 the following figure is present for c15 Register Bits

Figure 4-29 Secondary Auxiliary Control Register format

In Error Correction (C15, bit3), the label shown in the figure as B0TCMECC.

So, where is B1TCMECC bit?

Any information will help me.

Thank you.

Regards

Pashan

Hello Chuck,

Can you please provide exact details about which bits of either Cortex-R4 or TCRAMW has to be UPDATED when you say "disable ECC"?

This will definitely help me a lot to understand and change my testcase successfully.

Thank you.

Regards

Pashan

Hello Chuck,

In the Cortex-R4 r1p3 TRM of ARM, on Page 4-42 the following figure is present for c15 Register Bits

Figure 4-29 Secondary Auxiliary Control Register format

In Error Correction (C15, bit3), the label shown in the figure as B0TCMECC.

Can you please tell me what is the exact function of the above mentioned BIT in the system?

I thought ECC generation is done by TCRAM-Wrapper for every WRITE Cycle.

ECC Check is done by Cortex-R4.

So, what does the B0TCMECC bit does?

Thank you.

Regards

Pashan

Hello Chuck,

Thing are getting clear now.

So, when this BIT 3 is SET HIGH , then during read Single Bit Error, the correction will be done by the Cortex-R4 as well as ESM Single Bit Error will be generated if enabled at ESM Register?

Is the above statement correct

or only Single Bit Error will be corrected and no ESM error will be generated when Bit 3 is SET HIGH in BTCMECC field?

Thank you.

Regards

Pashan

Pashan,

As I follow the thread, it seems to wander a little. I'm not sure if what is asked relates to the initial question anymore? Does this thread reduce to the question:

"What things are necessary to correct single-bit errors from RAM and generate ESM errors?"

Regards,

Forum Support

Hello Support,

Yes, your question is right.

Also, when BTCMECC bit is HIGH [c15 bit 3], then only Single Error Correction is done by Cortex-R4 core. Under that condition also DATA ABORT occurs as well as ESM Error Interrupt is generated if enabled? or, only one of them, if so which one?

Is it valid for TMS570LS3137 as well as TMS570LSXXXX devices?

Thank you.

Regards

Pashan

Pashan,

The Second Auxiliary Control Register contains bits to correct and writeback the data to the RAM. These bits are c15 bits 1 and 3.

The Auxiliary Control Register contains a bit that enables the RAM external error enable (B0 and B1). These bits are c1 bits 2 and 1.

Suppose that the ECC errors are ignored (c1 bits 2 and 1 are cleared to o). Then errors are not detected.

Suppose that ECC errors are detected but not corrected (c1 bits 2 and 1 are set to 1 and c15 bit 3 is set). Then ECC errors are detected but not corrected. The result is that in the CPU's pipeline, when the error-flagged data is used (as data or opcode), the CPU generates an abort. The abort occurs for both single-bit and double-bit errors (because no correction is used). The ECC error is also flagged to the RAM wrapper, and the RAM wrapper can be configured to generate an ESM event on this error. Finally (for this case), when the ECC error is generated to the ESM, the address and data of the failing data is captured.

Suppose that ECC errors are detected and corrected (c1 bits 2 and 1 are set to 1 and c15 bit 3 is cleared). Then, single-bit ECC errors are detected and corrected. The result is that the error is flagged to the RAM wrapper and the wrapper can be configured to generate an ESM error and latch failing address and data. A double-bit ECC error is detected but cannot be corrected. The result is that the error is flagged to the RAM wrapper and the wrapper can be configured to generate an ESM error and latch failing address and data; additionally, the error-flagged data (either data or opcode) generates an abort when the CPU uses it.

For more information, please see the Cortex TRM as well as the RAM wrapper chapter in SPNU499 (Ch. 6).

Regards,

Forum Support

Hello Support,

Things are better understandable now.

My next question :

Assume BTCMRMW [c15 Bit 1] is HIGH.

Assume BTCMECC [c15  bit 3] is LOW.

When BTCMECC [c15  bit 3] is LOW, then error correction occur for Single Bit Error Type. I am assuming there is no typo in your last mail. I thought it was other polarity for this c15 bit 3. Please confirm if there is a typo.

This Single Bit Error Correction occurs during CPU READ from TCRAM also.

Is that correct?

That means suppose there is a single bit error within the ECC Space RAM [0x0840_0000].

CPU is reading 8-bit DATA [ using LDRB Opcode ] from 0x0800_0000 address.

Will the ECC Correction will trigger and correct the ECC Space RAM [0x0840_0000]?

Will the DATA ABORT trigger under the above mentioned LDRB Opcoe read from 0x08000_0000 address?

Thank you.

Regards

Pashan

Pashan,

The previous e-mail did have a typo.

I also answer your questions at the top:

1.) if a single bit error is detected anywhere within the RAM word (data OR ECC) AND correction is enabled, then the error is single-bit error is corrected.

2.) the address and data is sent to the RAM wrapper which can be configured to flag and latch failures. If the RAM wrapper flags the error, then the error is forwarded to the ESM which will generate an interrupt and possibly an ERROR pin toggle.

3.) In the case you have identified, no abort is generated becasue the error is corrected. When the data (opcode or data) gets executed, there is no error in the data.

The Second Auxiliary Control Register contains bits to correct and writeback the data to the RAM. These bits are c15 bits 1 and 3.

The Auxiliary Control Register contains a bit that enables the RAM ECC enable (B0 and B1). These bits are c1 bits 26 and 27.

Suppose that the ECC errors are ignored (c1 bits 26 and 27 are cleared to 0). Then errors are not detected.

Suppose that ECC errors are detected but not corrected (c1 bits 26 and 27 are set to 1 and c15 bit 3 is set). Then ECC errors are detected but not corrected. The result is that in the CPU's pipeline, when the error-flagged data is used (as data or opcode), the CPU generates an abort. The abort occurs for both single-bit and double-bit errors (because no correction is used). The ECC error is also flagged to the RAM wrapper, and the RAM wrapper can be configured to generate an ESM event on this error. Finally (for this case), when the ECC error is generated to the ESM, the address and data of the failing data is captured.

Suppose that ECC errors are detected and corrected (c1 bits 26 and 27 are set to 1 and c15 bit 3 is cleared). Then, single-bit ECC errors are detected and corrected. The result is that the error is flagged to the RAM wrapper and the wrapper can be configured to generate an ESM error and latch failing address and data. A double-bit ECC error is detected but cannot be corrected. The result is that the error is flagged to the RAM wrapper and the wrapper can be configured to generate an ESM error and latch failing address and data; additionally, the error-flagged data (either data or opcode) generates an abort when the CPU uses it.

For more information, please see the Cortex TRM as well as the RAM wrapper chapter in SPNU499 (Ch. 6).

Regards,

Forum Support

Hello Support,

When BTCMECC Bit is HIGH [c15 bit 3], then I understand that DATA Read by CPU will get corrected by the CPU within itself [Register].

But my question is whether ECC RAM Cell will get updated or TCRAM Cell will get updated when CPU is reading Wrong DATA and correcting it within it's Register?

Remember, CPU is not writing but reading from TCRAM. Under this condition what happens on the TCRAM cell contents during Single Bit Error Correction?

Thank you.

Regards

Pashan

Hello Pashan,

The sequence that happens when a single bit error is detected is the data is corrected by the CPU, stored in a local buffer within the CPU, corrected data is written back to the TCRAM, then corrected data read back from the local buffer of the CPU for use. This means the TCRAM cell is corrected leaving the ECC RAM alone.