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HalCoGen and dma support

Other Parts Discussed in Thread: HALCOGEN, TMS570LS3137

I don't now how to generate dma.h and dma.c using HalCoGen. I'm using HalCoGen version 3.01.01

The Help function of HalCoGen describes the dma.h file. But it is not generated. How can I generate it?

  • Hello Cor,

    Unfortunately, DMA drivers have not been fully implemented in HalCoGen at this time. However, there are examples in the help files that show examples of how to setup the DMA.h file, an example for configuring DMA control packets and an example of some mibspi DMA code. Although these are simply examples, you should be able to use these as a basis for writing your DMA drivers.

  • Thanks.

    I found the dma.h and dma.c files in the examples folder of HalCoGen.

    I copied them to my project and used the functions to enable the dma like the example. But it does not seem to work.

    The example is about the MIBSPI interface. I need the dma for the SCI. So I had to change some things. I'm afraid I mis something.

    So these are the steps I do to send some characters by the SCI using dma:

    1 - enable the dma using the dmaEnable() from dma.c

    2 - assigning request 28 (LIN transmit) to channel 0 using dmaReqAssign(0,28) from dma.c

    3 - create a control packet (see below)

    4 - set this control packet for channel 0 using dmaSetCtrlPacket(DMA_CH0) from dma.c

    5 - set the channel 0 for hardware requests usig dmaSetChEnable(DMA_CH0, DMA_HW) from dma.c

    6 - enable the SCI transmit interrupt

    Note that the SCI transmit does work when I write each byte to transmit to te TD register of the SCI by CPU.

    Maybe the control packet is not correct. This is how I make the control packet:

      g_dmaCTRLPKT.SADD      = sadd;              /* source address             */
      g_dmaCTRLPKT.DADD      = dadd;              /* destination  address       */
      g_dmaCTRLPKT.CHCTRL    = 0;                 /* channel control            */
      g_dmaCTRLPKT.FRCNT     = 1;                 /* frame count                */
      g_dmaCTRLPKT.ELCNT     = dsize;             /* element count              */
      g_dmaCTRLPKT.ELDOFFSET = 0;                 /* element destination offset */
      g_dmaCTRLPKT.ELSOFFSET = 0;                  /* element source offset      */
      g_dmaCTRLPKT.FRDOFFSET = 0;                  /* frame destination offset   */
      g_dmaCTRLPKT.FRSOFFSET = 0;                 /* frame source offset        */
      g_dmaCTRLPKT.PORTASGN  = 4;                 /* port b                     */
      g_dmaCTRLPKT.RDSIZE    = ACCESS_8_BIT;      /* read size                  */
      g_dmaCTRLPKT.WRSIZE    = ACCESS_8_BIT;       /* write size                 */
      g_dmaCTRLPKT.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
      g_dmaCTRLPKT.ADDMODERD = ADDR_INC1;         /* address mode read          */
      g_dmaCTRLPKT.ADDMODEWR = ADDR_FIXED;        /* address mode write         */
      g_dmaCTRLPKT.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */

    with sadd is address of a uint8_t array

    with dadd = (uint32_t)(&(scilinREG->TD))

    and dsize is the number of bytes to transmit.

    Is this correct? Can the DMA transfer bytes this way?

  • Hello Cor,

    You stated that you enabled the SCI interrupt but not the SET_DMA_TX bit. Below is an excerpt from the TRM section 25.5.2.1 regarding using DMA with SCI in single buffer mode.

    "In polling method, software can poll for TXRDY bit to go high before writing the data to SCITD register. CPU is unnecessarily overloaded by doing this Polling method. To avoid this user can use either Interrupt or DMA method. To use interrupt method SET TX INT bit should be set and to use DMA SET TX DMA bit should be set. Either an Interrupt or a DMA request is generated the moment TXRDY is set. When the SCI has completed transmission of all pending frames, the SCITXSHF register and SCITD are empty, the TXRDY bit is set, and an interrupt/DMA request is generated, if enabled. Because all data has been transmitted, the interrupt/DMA request should be halted. This can be done by either disabling the transmit interrupt (CLR TX INT) / DMA request (CLR TX DMA bit) or by disabling the transmitter (clear TXENA bit)."

    There is also additional information in section 25.4.regarding using DMA with the SCI module.

    If you want to use a combination of the interrupt and DMA, you could change the DMA transfer from HW to SW controlled and use software to initiate the DMA transfer for the next transmission within the ISR. This way, it might be easier to control the number of DMA transfers for a given set of message transmissions. Otherwise, if the interrupt isn't needed, you can set it up only for DMA transfers with HW triggering of the DMA.

  • Sorry that was an mistake of me.

    The line

    6 - enable the SCI transmit interrupt

    should be

    6 - enable the SCI transmit dma request

    In this step I write 1<<16 to the SCISETINT register to set the SET_DMA_TX flag and thus to enable the dma requests from SCI.

  • Hello Cor,

    Reading through the description in the TRM, it states that the DMA request will be initiated once TXRDY is set. Can you check to insure this is done?

  • Hello Chuck,

    Thanks for your reaction.

    I do not set the TXRDY myself, but after initializing the SCI, the TXRDY is indeed high. (writing a value to the TD register of the SCI does transmit a correct character).

    Also after initializing the dma, the control packet (primary CP0) in memory has been initialized. The values of the working CP0 on the other hand are all zero.

    Even after all 6 initialization steps, the working CP0 is zero. I assume this means that the DMA is not started.

    What else can I check?

  • I found out I made some stupid mistakes:

    1: element count should be 1 and frame count should be te number of bytes to transmit.

    2: dma request number 29 is the one for LIN transmit (not 28).

    But even with these corrections the transmit didn't work.

    Well..., I was thinking it didn't work because the working registers of the DMA control packet all stay zero.

    But the strange thing is that the bytes are correctly transmitted! So the DMA did work!

    So somehow the working registers (Current Source Address, Current Destination Address, Current Transfer Count) are not updated by the DMA controller.

    Is this a bug?

  • Hello Cor,

    I am glad to hear that you got this code working! The issue you are seeing with the working registers is that they are used by the internal logic of the DMA and are not CPU accessible which is why they will always read as 0. This is designed this way to improve the efficiency of the module and as intended by the design.

  • Does this mean there is no way to check the number of transferred elements?

    I now the maximum, so I set the element count to the maximum number.

    But I would like to see the actual number of transferred elements.

  • Hello Cor,

    I apologize for the lengthy delay in answering your last question. I think the thread below will help answer your question.

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/160798/585450.aspx#585450

  • Hello Cor,

    Were the answers provided within the thread sufficient to answer your questions? If so please verify the answers so that we may close the thread.

  • Dear friends,

    I try to use DMA with SCI2 (LIN) TX,

    However, I tried everything found from google search, including the questions and answers of this forum.

    uC is TMS570ls3137,

    tried the code 7633.sci_dma.zip downloaded from here. however, not successfull.

    In the datasheet it says:

    "Transmit DMA requests are enabled by the setting SET TX DMA and SET TX INT bits

    If the SET TX DMA bit is set, then a TX DMA request is sent to the DMA when data is written to SCITD

    and TXRDY is set.The DMA will write the first byte to the transmit buffer.

    ." section 27.4.2.

    But as I know DMA should be independent fron TX irq,

    thanks in advance.