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eFuse errors

Eugene K
Expert 1685 points

The initialization code from here http://focus.ti.com/mcu/docs/litabsmultiplefilelist.tsp?sectionId=96&tabId=1502&literatureNumber=spna106a&docCategoryId=1&familyId=1870 suggests the following:

      /* Check if there were ESM group3 errors during power-up.

      * These could occur during eFuse auto-load or during reads from flash OTP

      * during power-up. Device operation is not reliable and not recommended

      * in this case.

      * An ESM group3 error only drives the nERROR pin low. An external circuit

      * that monitors the nERROR pin must take the appropriate action to ensure that

      * the system is placed in a safe state, as determined by the application.

      */

      if (esmREG->ESTATUS1[2])

      {

            while(1);

      }

Could someone clarify the following?

  • ESM G3 contains other error bits - at least RAM ECC errors. Should they be masked out for auto load check?
  • After PORST RAM/Flash ECC error detection is disabled. Is it still possible that OTP ECC errors could set ESM bits?
  • Does eFuse auto load happen each reset (DWD, SW, nRST) or only during PORST?

Thanks,

Eugene

  • 0
    TI__Guru 59540 points

    Hello Eugene,

    I can understand the confusion here. Answers to your questions are below.

    • ESM G3 contains other error bits - at least RAM ECC errors. Should they be masked out for auto load check?
    • In general, when trying to differentiate between error types this is the best practice; however, in this case it is not needed because RAM ECC is not yet enabled. If you follow the flow of the startup sequence you will see that RAM ECC is enabled after the STC check which sequentially takes place after checking for the group 3 errors. From a different vantage point, even if an uncorrectable RAM ECC were to occur on startup it could still be a red flag for running the device and the application may still want to put the device in a safe state.
    • After PORST RAM/Flash ECC error detection is disabled. Is it still possible that OTP ECC errors could set ESM bits?
    • For the eFUSE and OTP loading, ECC is effectively forced to be enabled so these errors will be caught. This is a slightly different process than the standard ECC used during run time but with the same results.
    • Does eFuse auto load happen each reset (DWD, SW, nRST) or only during PORST?
    • eFUSE and OTP are loaded on startup only (i.e., PORST).

     

    In general, the recommended startup sequence is provided as a place to begin and shows the minimum set of start up tests that need to be ran in a safety related application. This by no means is an end all solution and should/can be modified to fit specific application needs. Also note that this code is provided as an example and has no implied warranty for use in a production system. The intent of this statement is that you should go through your normal due diligence to insure the code is robust and reliable for your application.