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12-bit ADC Frozen, 10-bit ADC Operational

Other Parts Discussed in Thread: HALCOGEN

Hi,

I am using the TMS570LS31x Hercules MDK.

I have 10-bit ADCs operating well. I require 12-bit ADC operation. I have made the following changes to convert from 10-bit to 12-bit ADC:

  1. Set bit '10/12 BIT' in ADC register ADOPMODECR to '1' (from '0').
  2. Modified the result register mask from 0x3FF to 0xFFF.
  3. Changed the ADC calibration mid reference point from 0x1FF to 0x7FF.
My problem is that the value read from the ADC channel is frozen at a single value (I am feeding a 1Hz sine wave into the ADC). Am I missing some subtle configuration that I haven't been able to locate in the documentation?
Regards, Tony.
  • Tony,

    I have been working with the ADC in 12-bit mode and do not think that there are any tricks here. (Your sequence sounds right, but obviously something is not working so I'll give you a couple of other ideas)

     

    If you are trying to convert while in debug mode, did you set the Continue-on-Suspend bit (COS)?

    If you are using a hardware trigger, make sure that the trigger gives enough time for the conversion to complete (i.e. a 12-bit conversion takes longer than a 10-bit conversion).

     

    My initialization of the ADC is shown below:

    Release ADC from Reset  (adcREG1->RSTCR = 0)
    Enable ADC s/m (w/ COS) and in 12-bit mode  (adcREG1->OPMODECR = 0x81000001)
    Prescale VCLK by (prescale +1) in order to create the proper ADCLK  (adcREG1->CLOCKCR = prescale)
    Set sample time  (adcREG1->G1SAMP = sample)
    Set discharge time  (adcREG1->G1SAMPDISEN = (discharge<<8) + 1)

    If conversions are triggered through a hardware trigger configure the group to accept the hardware trigger (GxMODECR) and select the trigger source (GxSRC)

    Select the channels in the group (GxSEL)

     

    If these ideas don’t help, please feel free to send a little more detail on your code setup…

     

    Regards,

    Forum Support

  • Hi Kevin,

    I still can't get it to work! I've attached a code snippet of my initialisation function. As I've mentioned, just changing regAdc1.ADOPMODECR.10/12 BIT from a 1 (12-bit) to 0 (10-bit) is sufficient for it to work in 10-bit mode!

    Any ideas will be gratefully received.

    Regards, Tony.

    Post-post note: I can't see the attached file. Can you see it?

  • Tony,

    I cannot see the file.

    Regards,

    Kevin Lavery

  • Regards, Tony.

  • Hi Kevin,

    I attached the code snippet in the previous post.

    I have loaded the Hercules Safety Demo and tweaked it so that the ADC tests run continually. It looks as though both 10-bit and 12-bit ADCs work here, and I toggle between them as described before.

    As this software works, it must just be a matter of going through and comparing register initialisations. I'll concentrate on this approach.

    Regards, Tony.

  • Tony,

    I actually cannot see the snippet. Can you re-post?

    Regards,

    Kevin Lavery

  • Hi Kevin,

    Third time lucky! Here it is:

    3465.AdcInitSnippet.txt

    Regards, Tony.

  • Hi Kevin,

    You will have noticed that I am triggering the Event Group off HET8, which has a rising edge every 62.4us. This all works fine for 10-bit ADC.

    I have EV MODE set to zero, i.e. single conversion on trigger. I have discovered that by turning on continuous conversion (EV MODE set to one), then I do get repeated 12-bit ADC readings.

    I can confirm that I do have an output from HET8, I can see it on my scope. So, how come these HET8 events trigger 10-bit conversions, but not 12-bit conversions?

    I don't think that there is an overrun in ADC conversion time, I think that for 24 conversions (i.e. all channels in the event group on ADC1) the time required is 12.96us for 10-bit and 14.4us for 12-bit. This is well short of the 62.4us HET8 period (which is at 50% duty).

    Regards, Tony.

  • Hi Kevin,

    Some further information:

    • I have doubled the period of my HET8 trigger from 62.4us to 124.8us; this makes no difference (12-bit ADCs are not repeatedly triggered by HET8).
    • I have reduced the number of conversions from 24 to 1; again this makes no difference.
    I think it must be something more fundamental than a timing issue.
    Have you any thoughts on the matter?
    Regards, Tony.
  • Tony,

    I was going to suggest what you have tried. I am successful in using the RTI to trigger 12-bit ADC, and the fact that your continuous mode works makes me think it is NOT  something too fundamental. I'll try again tomorrow to resolve.

     

    Regards,

    Kevin Lavery

  • Hi Kevin,

    I thought I would modify the TMS570LS3 Hercules Demo program to drive one of the ADC trigger HETs (e.g. HET8, HET10...) instead of one of the others it drives as part of the 'Running Light Balance', which seems to be the one that drives the HETs, but have been unsuccessful. I thought it would be a simple matter of changing the HET program in het.c to reconfigure the HET pins used for PWM output, so, for example, all uses of HET18 change to HET8.

    Presumably you have a little project of your own and can try 12-bit ADCs with HET trigger. If you can prove it on your configuration, you could then maybe send the project to me for me to try on my HDK?

    Regards, Tony.

  • Hi Kevin,

    Have you managed to get HET triggered 12-bit ADCs working?

    I'm not in work next week and am keen to resolve this before I go. I will be in work tomorrow.

    Regards, Tony.

  • Tony,

    I have triggered a single 12-bit channel. (On Sept 10, you indicated that even a single channel was not working.)

    The ADC init is:

    // start ADC
     adcREG1->RSTCR = 0; // Release ADC from Reset
     adcREG1->OPMODECR = 0x81000001; // enable ADC s/m (w/ COS) and in 12-bit mode
     adcREG1->CLOCKCR = prescale; // prescale VCLK by (prescale +1)
     adcREG1->G1SAMP = sample; // 2+sample ADCLK sample window
     adcREG1->GxMODECR[1] = (1<<3); //Set Group1 for hardware trigger
     adcREG1->G1SRC = ((1<<3)+1); // HET[8] as trigger source on rising edge
     adcREG1->GxSEL[1] = 0x01; // convert ADC channel 0

    The HET is initialized as follows:

        hetREG1->DOUT = 0;  /** - Set HET pins default output value */
        hetREG1->DIR = (1<<8); /** - Set HET pins direction */
        hetREG1->PDR = 0;     /** - Set HET pins open drain enable */
        hetREG1->PULDIS = 0; /** - Set HET pins pullup/down enable */
        hetREG1->PSL = 0;     /** - Set HET pins pullup/down select */
        memcpy((void *)hetRAM1, (const void *)HET_INIT0_PST, sizeof(HET_INIT0_PST));

        hetREG1->PFR = ((2 << 8) + 0);
        hetREG1->PRY = 0;
        hetREG1->INTENAC = 0xFFFFFFFF; // clear interrupt
        hetREG1->INTENAS = 0;

        hetREG1->GCR = 0x01030001U;

    and the HET code is:

    HET_MEMORY const HET_INIT0_PST[2] =
    {

      /* start_0 */
     {
      0x00002C20,
      0x0000052E,
      0x00000000,
      0x00000000
     },

      /* l02_0 */
     {
      0x00000100,
      0x00400858,
      0x0000FA00,
      0x00000000
     }
    }

    The code runs at 170MHz; VLCK2 is set to HCLK/2 and the simple HET code I have has a loop resolution prescale of 4 (so that every loop of the HET executes at 85MHz/4). The CNT instruction is set so that HET[8] generates a rising edge every 62.4us.

     

    Regards,

    Kevin Lavery

  • Hi Kevin,

    I'm just back in the office today, hence my tardy response.

    I now have 12-bit ADCs working, so thanks for your help with that.

    It appears that the setting of '10/12 BIT' in ADOPMODECR must be performed pretty early. I was setting it after my group configuration (as you will see in my code snippet). You and HALCoGen both set '10/12 BIT' immediately after resetting the ADC module.

    I have now done this and it all works. I have deferred my enable of the ADC module ('ADC EN' in ADOPMODECR) until after group configuration as in HALCoGen, rather than at the same time as '10/12 BIT' configuration as you have done.

    I couldn't find anything in the TRM that says '10/12 BIT' must be set before any other particular configuration. I suggest that something be added to the TRM to indicate this.

    Thanks again, Tony.