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EMIF - Finish of read/write cycle according to WAIT signal

Petr Burian
Prodigy 70 points

Hi,

I use EMIF periphery with WAIT signal. I would like to know how many emif clock cycles after deactivation of the WAIT signal is read/write cycle terminated.

I am tested it and it seems that read/write cycle continues several clock cycles after WAIT .

BTW: Is not error in the reference manual ? I used the following setting:

emifREG->AWCC  = emifREG->AWCC| 
                      emif_pin_low << 29| 
                     emif_pin_low << 28| 
                     emif_wait_pin0 << 16| 
                     127; 

However, the processor inserts wait cycles when WAIT signal is high.

Thank you.

PS: The figure from analyzer is attached.

  • 0
    TI__Guru 68920 points

    Hi Petr,

    Sorry for the long delayed response.

    In case the question is still relevant (or if anyone else has the same question) the answer is found in this section of the datasheet:

    The strobe has to be deasserted for at least two clock cycles, there may be just under two additional cycles worth of strobe (depends on where the

    strobe deassertion falls relative to the internal EMIF clock.)  And then the EMIF moves into the HOLD phase during which the strobe is deasserted.