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Can't enter Debug mode with Ti TMS570LS10116

Lin Trevor
Prodigy 100 points

Other Parts Discussed in Thread: TMS570LS10106

Hello there,
This is Trevor from System General, a leading supplier in IC programmer. I have a question regarding debug mode on TI TMS570LS10116.

After device power on, turn on clock, deassert power on reset, external host issue five TCK cycles with DBGTMS HIGH, and issue IR instruction 0xE but the device always got NO response  (should get JTAG ID from the device!)

Would you please help us to identify whether below spec can apply to TI TMS570LS10116? I assume this part should refer to ARM Debug Interface v5 Architecture Specification as below link indicates.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0031a/index.html
  • 0
    TI__Mastermind 23000 points

    Hello Trevor,

    Please reference the debug subsystem noted in section 4.8 of the product datasheet:  http://www.ti.com/litv/pdf/spns141f.

    The TI ICEPICK scan chain router is the logic present with direct connection to the JTAG interface.  To access the ARM DAP, you must first configure ICEPICK to route the scan chain to debug scan chain #0.  Once you have the ARM debug logic in the scan chain, you can apply the details found in the ARM document.

    As noted in the product datasheet, the 32b JTAG ID code for the product is 0x0B7B302F.

    Best Regards,

    Karl

  • 0 in reply to KGreb
    Prodigy 100 points

    Hi Viki ,Karl
    thanks for your support .
    after follow your suggest .
    ( Host select scanchain #0 before issue IDCODE instruction )  
    It's doesn't working .
    below is detail descrption .

    01. set_TEST(0) ;
    02. Power up TMS570LS10106 Vdd ( 1.5 volt ) ;
    03. Power up TMS570LS10106 Vcc ( 3.3 volt ) ;
    04. set_nPORRST0); delay 10ms ;
    05. set_nPORRST(1); delay 10ms ;
    06. set_nRST(0); delay 10ms ;
    07. set_nRST(1); delay 10ms ;
    08. set_nTRST(0); delay 10ms ;
    09. set_nTRST(1); delay 10ms ;
    11. tap_state_machine_reset();



    12. select_IR();

    13. issue(PRELOAD);

    14. select_DR();

    15. issue(0x0);

    16. return_IDLE();

    17. select_IR();
    18. issue(0xE);

    19. select_DR();
    20. Get_IDCODE();
    after step 20 , device doesn't have any response .
    it's should be response IDCODE .
    which step are wrong , please tell me , thanks .

    Best Regards,

    Trevor

  • 0 in reply to Lin Trevor
    TI__Mastermind 23000 points

    Hello Trevor,

    Do you have past experience working with the TI ICEPICK module?  It is not so simple as to just input scan chain #0.  There are configuration commands which must be given to the ICEPICK.  Some basic details can be found here:  http://processors.wiki.ti.com/index.php/ICEPICK and in particular in this file: http://processors.wiki.ti.com/images/3/3c/Router_Scan_Sequence.pdf

    Regards,

    Karl

  • 0 in reply to KGreb
    Prodigy 100 points

    hello Karl
    After reading all of linking of
    http://processors.wiki.ti.com/index.php/ICEPICK
    I know must be utilize the scan sequences to get ICEpick to setup the R4 into the scan chain first.
    after this, I has got connected to the ARM Cortex R4.

    I have many question to ask you reply .
    1.Which category ( ICEPick-B, ICEPick-C, ICEPick-D ) is TMS570LS used ?
    2.Which pin has functions like EMU0 & EMU1 on TMS570xxxx .
    3.in Router_Scan_Sequence.pdf , it's talking about TAP port address,
      Would you give more descrption ( or documents ) about TAP port address.
    4. if Ti have more documents talking about ICEpick on TMS570LS , please let me know .
       I think just previous information , isn't enough 3rd party developer emulator .   

    Thank you for all your assistance.
    Greatly thank you again for your assistance.

  • 0 in reply to Lin Trevor
    TI__Mastermind 23000 points

    Hello Trevor,

    1.  ICEPICK-C is present on the TMS570LS family, as noted in product documentation.

    2.  There are no EMU0/EMU1 pins on the TMS570LS family.  These pins are not standard for JTAG standard nor most ARM devices.  What functions are you trying to use?

    3.  Debug TAP #0 is ICEPICK TAP #16, Debug TAP#1 is ICEPICK TAP #17, ...

    4.  We have not had issue for multiple developers to create products using this documentation.  If further assistance is required, this has been available in the past from TI SDO (tools group) through the developer network under NDA.

    Regards,

    Karl

  • 0 in reply to KGreb
    Prodigy 100 points

    hello Karl
    After reference another chip ICEpick Module ,
    I still can't access ARM core.
    but I am be able to get IDCODE, ICEPICKCODE, USERCODE .
                         ( 1B7B302F, 2E121CC2, 80206D0D )
    Would you help us to check below program sequence is correct or not ?
    below script is J-link IcePick setup file ,
    I think that is same as TMS570LSxxx .
    please help us to modify below script for TMS570LSxxx ..

    Thanks,

    Trevor

    //
    // J-Link Target setup file for IcePick on TI OMAP L138
    // Note that a very similar init works for other TI devices. In case of of doubt, please contact support@segger.com
    //
    //Dialog.MessageBox("Setting up Icepick");
    //
    // Setup Icepick
    //

    // In order to use the "WriteIR" and "WriteDR" commands,
    // IRLen of device has to be set first.
    // If you have multiple devices in the scan chain at boot up time
    // IRPRE, DRPRE, IRPOST and DRPOST have also be set in order to use the "WriteIR" and "WriteDR" commands
    //
    JTAG.IRLen=6;
    JTAG.Speed = 1000;                   // Set high JTAG speed
    //
    // JTAG.Write Syntax JTAG.Write(NumBits, <TMS>, <TDI>)
    //
    JTAG.Write  (6, 0x1F,0x1F);          // TAP Reset
    JTAG.WriteIR(7);
    //
    // JTAG.WriteDR Syntax JTAG.WriteDR(NumBits, <TDIData>)
    //
    JTAG.WriteDR(8, 0x89);
    JTAG.WriteIR(2);
    JTAG.WriteDR(32, 0x81000080);
    JTAG.WriteDR(32, 0xA000206F);
    JTAG.WriteDR(32, 0xA000216F);
    JTAG.WriteIR(0x3F);                  // Bypass
    JTAG.Write  (10,0,0);                // Write 10 clocks

    //
    // Configure JTAG chain, so J-Link knows to which devices it has to "talk"
    //
    JTAG.IRPRE=0;
    JTAG.DRPRE=0;
    JTAG.IRPOST=6;
    JTAG.DRPOST=1;
    JTAG.IRLen=4;
    CPU=arm926ejs;

  • 0 in reply to Lin Trevor
    TI__Mastermind 23000 points

    Hello Trevor,

    I am not familiar with the J-Link product nor its scripts, but the script shown appears to be for an ARM 9 class product.  You need to configure your script to access the ARM DAP (more specifically the JTAG-DP) after you have initialized ICEPICK.  The ARM CoreSight Components TRM has details on the DAP and JTAG-DP registers:  http://infocenter.arm.com/help/topic/com.arm.doc.ddi0314h/DDI0314H_coresight_components_trm.pdf

    I'd start by trying to get the IDCODE out of the JTAG-DP, the working on scans for the Cortex R4 once you are sure you have both ICEPICK and the ARM JTAG-DP working.

    Regards,

    Karl