Multiple Appearance of Pins in IOMM PINMMRnn: Pin Multiplexing Control Registers

Tony Morrell

Hi,

In the TMS570LS31x/21x Technical Reference Manual (SPNU499), several pins appear within more than one IOMM PINMMRnn registers. I wondered why this might be.

The pins in question are:

MIBSPI1SIMO[1] in PINMMR14[01] and PINMMR13[25]
N2HET1[17] in PINMMR20[17] and PINMMR24[16]
N2HET1[19] in PINMMR08[09] and PINMMR24[24]
N2HET1[21] in PINMMR09[25] and PINMMR25[00]
N2HET1[23] in PINMMR12[17] and PINMMR25[08]
N2HET1[25] in PINMMR07[09] and PINMMR25[16]
N2HET1[27] in PINMMR00[26] and PINMMR25[24]
N2HET1[29] in PINMMR00[18] and PINMMR26[00]
N2HET1[31] in PINMMR09[10] and PINMMR26[08]
SPI4CLK in PINMMR05[01] and PINMMR23[08]
SPI4NCS[0] in PINMMR04[25] and PINMMR24[08]
SPI4NENA in PINMMR04[17] and PINMMR24[00]
SPI4SIMO in PINMMR05[09] and PINMMR23[16]
SPI4SOMI in PINMMR05[17] and PINMMR23[24]

Regards, Tony.

over 13 years ago

0 Sunil Oak over 13 years ago

TI__Mastermind 49120 points

Hi Tony,

The MIBSPI1 signals are two distinct signals: SIMO[1] and SOMI[1], and have two separate controls.

The rest of the signals in your list indeed have two separate control bits. This is mainly to be able to select the input paths for these signals. Consider the SPI4CLK example shown on page 257 of SPNU499. This MCU has a dedicated SPI4CLK I/O pad which is not bonded out in either the available PGE or the ZWT packages. However, the default input to the SPI4 module for SPI4CLK comes from this dedicated pad. So if you want to use the multiplexed SPI4CLK terminal, you would need to select the correct input path by configuring the PINMMR5[1] and PINMMR23[8] registers. The example shows how PINMMR5[1] and PINMMR23[8] are used to select the input path for the SPI4CLK signal. Please note that there is an error in the logic equation shown for selecting the input path.

The correct equations are:

Input path from dedicated pad is selected if not(A) or (A and B) = 1

Input path from multiplexed pad is selected if A and not(B) = 1.

This correction is being made to the next update of the TRM.

Regards, Sunil

0 Chuck Wong over 11 years ago in reply to Sunil Oak

Genius 3950 points

Hi Sunil,

if I take as an example the SPI4CLK from the multiplexed input, I would set the following to satisfy A and not(B) = 1:

PINMMR5[1] = 1

PINMMR23[8] = 0

Should I also clear PINMMR5[0] = 0 to deselect the existing default function for N2HET1[0], or I solely have to make sure that A and not(B) = 1, and any other pin sharing the multiplexed input would be automatically deselected?

Thanks.

0 Sunil Oak over 11 years ago in reply to Chuck Wong

TI__Mastermind 49120 points

Hi Chuck,

PINMMR5[0,1] control the signal that will be output on the terminal shared by N2HET1[0] and SPI4CLK. For selecting this terminal to be the input path for SPI4CLK it is enough to configure PINMMR5[1] = 1 and PINMMR23[8] = 0.

This could be a problem if software accidentally configures N2HET1[0] to be an output pin. That is why it is safer to clear PINMMR5[0], although it is not required to get SPI4CLK input from the shared terminal.

Regards, Sunil

P.S.: Please refrain from adding new questions to forum posts that have already been answered and closed. Start a new thread even if it is somewhat related to an earlier post. You can always add on to a thread that is currently active. This will help us keep better track of open threads and respond in a timely manner.

0 Chuck Wong over 11 years ago in reply to Chuck Wong

Genius 3950 points

Hi Sunil,

I understand what you're saying but I still have questions on the IOMM ... I'll open a new thread.

Thank you!

Arm-based microcontrollers

Arm-based microcontrollers forum

Multiple Appearance of Pins in IOMM PINMMRnn: Pin Multiplexing Control Registers