I am working with identical boards using LX4F232H5QC A3 chips and emulating using CCS 5.2 and a XDS560v2. Three of the five boards have a problem. I have specifically set PA6 to interrupt when PA6 is low. This is how the two 'working' boards interrupt. On the offending boards I am analyzing, I 'CPU reset' from the debug tab, then I see in the CCS Registers window that PA0 is set to interrupt on low and both edges: GPIO_IBE: 0x00000001, GPIO_IM: 0x00000001.
But these conditions are causing continuous interrupts on PortA. PA0 is configured for CAN. My apps initilization code should be irrelevant as I am looking at port registers at setup.
Is this a problem with A3 silicon?
Errata says nothing about interrupts or PA0. What it does say about Port A should be fixed in A3 silicon. Data Sheet says the bits I am worried about should be cleared on reset and hence I should not be seeing this.