EMIF CLK output - in asynchronous mode

Peter Martin

Other Parts Discussed in Thread: RM48L952, RM48L950

Hi,

I am using the EMIF to implement a memory mapped 16 bit connection to a FPGA. I have decided on Asynchronous mode for simplicity, because speed is not critical and to keep the FPGA design simple.

It is clear from reading the TRM that the asychronous mode timing is actually derived from the EMIF_CLK frequency. This is not shown explicitly in the device data sheet.

My question is simply whether the EMIF_CLK is output on a pin when in asynchronous mode, and if so is it continuous?

Thanks in anticipation.

Best wishes

Peter

over 13 years ago

0 Jean-Marc Mifsud over 13 years ago

TI__Mastermind 22375 points

Peter,

Thanks for using our forum.

To better answer your question, which device are you using?

0 Peter Martin over 13 years ago in reply to Jean-Marc Mifsud

Prodigy 200 points

Sorry, I assumed that the EMIF block would be common throughout the RM48 family.

It is the RM48L950 / RM48L952 in the ZWT 337 BGA package.

Best wishes

Peter

0 Jean-Marc Mifsud over 13 years ago in reply to Peter Martin

TI__Mastermind 22375 points

Peter,

On RM48L950, there is a dedicated pin for EMIF_CLK. (Bal K3 on the 337BGA)

Internally, EMIF_CLK is free running clock.
To reduce emission, this signal is gated off by default (tri-stated.)

If you want to see/use EMIF_CLK externally, PINMUX29[8] must be cleared to enable this output.

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EMIF CLK output - in asynchronous mode