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ESMSSR2 Power On Reset value

Hello Support,

ESMSR2 Register is reset to ZERO value under following RESET Conditions :

1> PORRST Pin -- PORRST Bit of SYSESR

2> nRST Pin -- EXTRST Bit of SYSESR

3> WDRST Bit of SYSESR

4> SWRST Bit of SYSESR -- Triggered by SYSECR Register

5> CPURST Bit of SYSESR -- Triggered due to LBIST or MMUGCR Register

6> OSCRST Bit of SYSESR -- Triggered due to FMzPLL PLLSLIP Bit

Is the above statement correct?

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ESMSSR2 Register [Shadow of ESMSR2] is reset to ZERO value only during PORRST Bit of SYSESR Register.

Is the above statement correct?

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Please answer separately for each of the above questions.

Thank you.

Regards

Pashan

 

  • pashan,

     Your observations are correct for both ESMSR2 and its shadow register ESMSSR2 regarding the reset sources .

     

    TI forum support

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