Hello TI Experts,
in TRM of TMS570PSFC62, in the section SECDED support (4.3.1), it states:
"It is the master's responsibility to maintain integrity between the data and its ECC for all operations". I am not clear what this mean.
In a case that when a ESM R4 SEC event occur (threshold set to 1) to indicate there is a single bit error in RAM due to a RAM read (or a RAM DMA channel transfer), is application software responsible to get to the RAM location to correct the error bit or it is corrected automatically by ECC SEC functionality so that next RAM reading at the same location will get the correct value?
Currently, our software go to error location from Single Bit Error Address Register and do a read and write to correct the error. I am wondering if this is needed if ECC SEC functionality will correct the error in RAM location for the next reading.
Thank you.
Joy
