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Stellaris Watchdog 1 Setup



I'm trying to use the watchdog timers on the lx4f230h5qr.  Watchdog0 seems to work, but Watchdog1 doesn't.

 

I'm enabling power to both 0 and 1 using SYSCTL_PCWD_P0

I'm enabling clock to both 0 and 1 using SYSCTL_RCGCWD_R

I'm resetting and then un-resetting both 0 and 1 using SYSCTL_SRWD_R

I'm watching SYSCTL_PRWD_R to see them indicate they are alive and I see Watchdog0 is ok, but Watchdog1 is not.

I can access WATCHDOG0_CTL_R, but when I attempt to read WATCHDOG1_CTL_R, I get a fault interrupt.

This seems to be the case whether I am running the system clock from PIOSC or an external clock source on Main OSC.

 

What are the steps necessary to get the watchdog 1 to function 

  • Charles Smith said:

    I'm enabling power to both 0 and 1 using SYSCTL_PCWD_P0

    I'm enabling clock to both 0 and 1 using SYSCTL_RCGCWD_R

    Without seeing your code it's hard to verify that in fact you are doing what you say you are.  In particular, if you are using the blinky example as a template for direct register writes, you are probably making a basic mistake that most people make in the enabling and configuring of peripherals.

  • Hi Charles,

    Looking through the datasheet I found this note about using watchdog timer 1 (http://www.ti.com/lit/ds/spms314d/spms314d.pdf - found on pg. 754 and 758):

    "Because the Watchdog Timer 1 module has an independent clocking domain, its registers must be written with a timing gap between accesses. Software must guarantee that this delay is inserted between back-to-back writes to WDT1 registers or between a write followed by a read to the registers. The timing for back-to-back reads from the WDT1 module has no restrictions.

    The WRC bit in the Watchdog Control (WDTCTL) register for WDT1 indicates that the required timing gap has elapsed. This bit is cleared on a write operation and set once the write completes, indicating to software that another write or read may be started safely. Software should poll WDTCTL for WRC=1 prior to accessing another register. Note that WDT0 does not have this restriction as it runs off the system clock and therefore does not have a WRC bit."

    Please let me know if you need any clarification or help with this issue.

    Thanks,

    Clinton

  • For those looking into this issue, Charles and I had some discussion offline on this topic. Relevant info can be found below:

    He is aware of the different clock domains and suspects this may be related to the problem. He clarified that the SYSCTL_PRWD_R register problem occurs before the Watchdog registers are accessed and the fault interrupt can happen before any writes to the WDT1 registers have been attempted.

    Thanks,

    Clinton

  • Hey Charles,

    Attached is a working program showing how to use the WDT's.  Let me know if this helps or not.

    Thanks,

    JD