Error 0x80000244/-2131

This sounds like the problem that was found on this CCS release 4.1.3 in 2010.

In the below picture (CCS4.1.3), please check the box in front of Pseudo Address to connect to the device.

Santosh,

What is the status on your question?
Did we answered it?

If so, can you please mark our answer as "Verified Answer" so we can close this post.

I tried checking the Pseudo address option. But it still gives the same error message. here is the screen shot of my target configuration

i have even tried to debug by changing the Type feild to legacy and virtual, all gives the same error message.

i have checked the debug lines on a oscilloscope. it seems TCLK is ok, other lines are varying but i don't know whether they are proper.

Could U help me with the timing diagram of the debug signals  TRST, TCLK, RTCLK, TMS, TDI, TDO

Which board are you using? From TI or built by yourself?

If you made it yourself, Please make sure the CPLD(if there are any) and EEPROM were programmed correctly.

I recommend you to update your CCS to most recent version, CCS5.2, because we dont have the enviroment to help you debugging.

I am using a custom board and xds100v2 emulator. I dont have any cpld or eeprom in my board. it directly connects to xds100v2 jtag signal lines.

can u send me the jtag signal timing diagram.

is CCS5.2 available for download. if so where can i get it.

Can you send me the schematic of MCU and FTDI chip?

I think the CPLD is OK to removed but the EEPROM is necessary. Otherwise, the CCS can not recognize this as the the xds100v2.

Haixiao

CCS download site: http://processors.wiki.ti.com/index.php/Download_CCS

I downloaded and installed CCS 5.2.1.0001

In the target configuration i selected TMS570LS20216SPGE which is my target controller.

I tried the "Test Connection" the following is the test report i got

//****************************************************************************************************************************

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity

[Result]


-----[Print the board config pathname(s)]------------------------------------

C:\Users\user1\AppData\Local\.TI\213602635\
    0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------

This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'May 30 2012'.
The library build time was '22:52:27'.
The library package version is '5.0.747.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------

The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[The log-file for the JTAG TCLK output generated from the PLL]----------

There is no hardware for programming the JTAG TCLK frequency.

-----[Measure the source and frequency of the final JTAG TCLKR input]--------

There is no hardware for measuring the JTAG TCLK frequency.

-----[Perform the standard path-length test on the JTAG IR and DR]-----------

This path-length test uses blocks of 512 32-bit words.

The test for the JTAG IR instruction path-length failed.
The JTAG IR instruction scan-path is stuck-at-zero.

The test for the JTAG DR bypass path-length failed.
The many-ones then many-zeros tested length was -16384 bits.
The many-zeros then many-ones tested length was 9344 bits.

-----[Perform the Integrity scan-test on the JTAG IR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 1, skipped: 0, failed: 1
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 2
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 3
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 4
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 5
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 6
Some of the values were corrupted - 82.9 percent.

The JTAG IR Integrity scan-test has failed.

-----[Perform the Integrity scan-test on the JTAG DR]------------------------

This test will use blocks of 512 32-bit words.
This test will be applied just once.

Do a test using 0xFFFFFFFF.
Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 1: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 2: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 3: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 4: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 5: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 6: scanned out 0xFFFFFFFF and scanned in 0x00000000.
Test 1 Word 7: scanned out 0xFFFFFFFF and scanned in 0x00000000.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 1, skipped: 0, failed: 1
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 1
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 2
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 3
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 4
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 5
Some of the values were corrupted - 83.3 percent.

The JTAG DR Integrity scan-test has failed.

[End]

//*********************************************************************************************************************************************

still unable to connect to my Tms570 device.. any help is much appreciated....

thank u

I tried re-programing my eeprom but the staus is same..

when i tried to monitor my jtag signals, i found that the TDO line is only at 200mV. my schematic connections are straight forward. The JTAG signal lines from my TMS570device i.e., TMS, TCK, RTCK, TDO, TDI, NRST, 3.3V, GND,  connect to the XDS100V2 - 14Pin connectors JTAG Signals. i verifed my hardware  and every thing is fine. i just want to know the levels of JTAG signals escpecially TDO line at the power on reset and the timing diagram for the JTAG period.

i am waiting for the reply.. my project is on hold because of this problem. any help is most welcomed and much appreciated...

as u requested my schematic i am posting my jtag and power ckt here

I did not find anything wrong in this schematic (It is vague).

TDO is the output of the MCU, can you check if it is shorted to the adjacent pin in MCU side or in the JtAG side?

Regards,

Haixiao

Yes i checked.. even i tried testing 2nd board.. faced the same problem.. i could only suspect 2 things now, either my xds100v2 should be bad or the controllers i got as samples from TI... is there any selftest procedure for XDS100V2 to check its functionality.....

Can you post your xds100v2 eeprom file, and the schematic?

Or send to haixiao.weng@ti.com

I can take a look.

Haixiao

Please make sure:

nPORRST pin is 3.3v

nRST pin is 3.3v

TEST pin is 0v