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What is the OTP Address for Checking Flash ECC Error Logic?



Hello Support,

In spnu516.pdf, I find the following section :

--------------------------------------------------------------------

4.5.1 Error Checking at Power On

As the device is coming out of the device reset sequence the flash wrapper reads two configuration words

from the TI OTP section of bank zero. During these reads ECC is enabled. Single bit errors are corrected

and uncorrectable errors will generate an ESM group 3 channel 7 error event. The ERROR pin

----------------------------------------------------------------------

What is the OTP Address for Checking Flash ECC Error Logic?

Thank you.

Regards

Pashan

 

  • Hi Pashan,

     

    Please reference SPNA106A, which is the example initialization code for the Hercules family.

    http://www.ti.com/mcu/docs/litabsmultiplefilelist.tsp?sectionId=96&tabId=1502&literatureNumber=spna106a&docCategoryId=1&familyId=1931

     

    From the file sys_startup_recommended.c, you will see the following

    #define flash1bitError (*(unsigned int *) 0xF00803F0)

    #define flash2bitError (*(unsigned int *) 0xF00803F8)

     

    Regards,
    Eric

     

  • Hello Eric,

    In the following link :

    http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/117842.aspx

    it is mentioned that :

    "For devices that does not support diagnostic mode there are reserved location within OTP which are delirabetely programmed to have single-bit and double bit errors , which could be used for failure checks."

    Now, in the spnu516.pdf for RM42 device, I see the following section which indicates this device does have FLASH DIAGNOSTIC MODE as shown below :

    So, does it also have OTP for Flash ECC Logic Check? But the previous mail from Pratip tells me different.

    May be my understanding is wrong.

    Please elaborate more between two mail's discrepancy.

    Thank you.

    Regards

    Pashan

     

    -------------------------------

    4.6.2 Diagnostic Mode

    Flash wrapper can be put in diagnostic mode to verify various logic. There are multiple diagnostic modes

    supported by the wrapper. A specific diagnostic mode is selected via the DIAGMODE control bits in the

    diagnostic control register (FDIAGCTRL).

    -------------------------------------------

     

  • Pashan,

    I think Pratip's comment is perhaps referencing legacy devices.  The latest RMxx devices which you are referencing have both the diagnostic mode and will also ship with the single and double bit errors programmed in OTP. 

    There is a reason for this.  The diag mode will test bus1 ECC errors in main flash (through mirrored flash locations).  This ECC is calculated inside the CPU ECC logic.  The OTP is on a separate bus (bus2), and performing the OTP test checks the ECC at the flash wrapper level.  In the SPNA106a example init code, please reference checkFlashECC(), which is for the main bus1 flash check using diag mode and mirrored flash.  Also, please reference fmcECCcheck() which tests ECC through bus2 at the wrapper level.

    Regards,
    Eric

  • Hello Support,

    I find the following in spna106a.zip -- sys_startup_recommended.c module :

    #define flashBadECC     (*(unsigned int *)0x20080000)

    Can you please tell me whether there is an intentional ECC Error created within the Flash Space while programming the Microcontroller usng nowFlash Tool?

    Or, this is a predefined address location which will always have ECC error?

    Thank you.

    Regards

    Pashan

     

  • Pashan,

    This location is in the mirrored flash address space.  It is not programmed into main flash as an error.  This is the check which uses the diagnostic mode to corrupt ECC (through Mirrored Flash access). 

    Please see the checkflashECC() function.  Diagnsotic mode 7 is a special mode which allows for creating of ECC errors through mirrored flash accesses (test purposes only). 

    Also note, there is a bug in this section of code.  Please change the following line ('4' to 'A'):

    910         flashWREG->FPAROVR = 0x00005A01;                                    // Select ECC diagnostic mode, single-bit to be corrupted

    Regards,
    Eric

    void checkFlashECC(void)

    {

    /* Routine to check operation of ECC logic inside CPU for accesses to program flash */

    volatile unsigned int flashread = 0;

    flashWREG->FEDACCTRL1 = 0x000A060A; // Flash Module ECC Response enabled

    flashWREG->FDIAGCTRL = 0x00050007; // Enable diagnostic mode and select diag mode 7

    flashWREG->FPAROVR = 0x00005401; // Select ECC diagnostic mode, single-bit to be corrupted

    flashWREG->FDIAGCTRL |= 0x01000000; // Set the trigger for the diagnostic mode

    flashread = flashBadECC; // read a flash location from the mirrored memory map

    flashWREG->FDIAGCTRL = 0x000A0007; // disable diagnostic mode

  • Eric,

    Does the flashBadECC value has to be that FIXED Address or it can be anything within the Mirror Flash Address SPACE?

    Thank you.

    Regards

    Pashan

     

  • Pashan,

    No, this is not the only address that can be used as any address can be used in the mirrored space.  However, the address and corresponding programmed ECC value play a role.  This has already been worked out for proper use in the Diag mode = 7 example code by using the correct DAT_INV_PAR value (which may make an assumption that this flash locations ECC is erased to 0xff).  If you plan to change to a different address, just make sure that you are creating the desired errors in this diag mode.  Please reference the LS12xx TRM, SPNU515, section 5.6.2.  The steps are highlighted in section 5.6.2.6. You may also want to reference the Syndrome Table in section 5.3.3

    http://www.ti.com/lit/ug/spnu515/spnu515.pdf

    Regards,
    Eric

  • Pashan,

    Also note that the address 0x20080000 is out of range for the TMS570LS04x device so you will need to assign a new address for this test on that device.