EMIF Asynchronous speed

ALLEN POETZSCH

Other Parts Discussed in Thread: HALCOGEN

I am trying to benchmark the Hercules performance for a project that I am working on and I can't seem to get the EMIF access time to be fast enough. It seems to be taking about 365nS for a single 16 bit access (and 750 for a 32bit).

I am using async access and the clock is set for 100MHz, with all setup and holds set for 0. Is there something that I am missing?

over 13 years ago

0 Zhaohong Zhang over 13 years ago

TI__Mastermind 22715 points

Allen,

Take a look at this thread.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/211679.aspx

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

Zhaohong Zhang said:

Allen,

Take a look at this thread.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/211679.aspx

Thanks and regards,

Zhaohong

Zhaohong Zhang said:

Allen,

Take a look at this thread.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/211679.aspx

Thanks and regards,

Zhaohong

Zhaohong

I don't think this helps. My problem is that the access is really slow. It appears to take 365nS for a single 16bit access or 750nS for a 32 bit (double 16 bit) acess. The EMIF clock is set for 100MHz. The math doesn't appear t owork out correctly.

Thanks

Allen

0 Zhaohong Zhang over 13 years ago in reply to ALLEN POETZSCH

TI__Mastermind 22715 points

Allen,

I would suggest you measure the signal on the EMIF CLK pin to see if it is really 100 MHz. What are your other clock settings (HCLK and VCLK)?

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

I am using the RM48 HDK and don't see where I can see the EMIF Clock signal on this board

0 Zhaohong Zhang over 13 years ago in reply to ALLEN POETZSCH

TI__Mastermind 22715 points

Allen,

EMIF clock is a continuous clock. You can see from SDRAM.

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

The SDRAM is a BGA part. Can you give me another lcation to look at the EMIF Clock

0 Zhaohong Zhang over 13 years ago in reply to ALLEN POETZSCH

TI__Mastermind 22715 points

Allen,

You can view EMIF CLK on resistor R41(see page 3 of HDK schematic). I think that there is something wrong in the way you set up the clocks. If you can share the information about how the clocks (I mean all the clocks) are set up in your application, we may be able to take a look. You can also set up ECLK pin to monitor different clocks.

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

The clock is only running at 8MHz..

0 ALLEN POETZSCH over 13 years ago in reply to ALLEN POETZSCH

Prodigy 245 points

HalcoGen indicates that the EMIF clock should be 100MHz. What should I look at to determine where the problem is

0 Zhaohong Zhang over 13 years ago in reply to ALLEN POETZSCH

TI__Mastermind 22715 points

Allen,

I am not sure how you set up this 100 MHz EMIF CLK.

There is a 16 MHz crystal at HDK. You need to first set up PLL to generate a PLL clock at higher frequency (180 MHz for example) from 16 MHz input. then you have select PLL clock as system clock. You can derive a 90 MHz EMIF clock by dividing system clock by 2. Halcogen is only a tool for generating configuration code with a graphic interface. You can see the clock tree in the datasheet and the system registers related to PLL and clock settings in the TRM.

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

I had the PLL setup for 200MHz. If I slow it down to 180MHz (so now the EMIF clock is 90MHz), then it appears to work OK

0 Nishant Garg over 13 years ago in reply to ALLEN POETZSCH

TI__Intellectual 3000 points

Zhaohong,

Are there any known issues with running the DK-EVM at full speed (200MHz)?

Thanks,

Nishant

0 Zhaohong Zhang over 13 years ago in reply to Nishant Garg

TI__Mastermind 22715 points

Nishant,

I have not heard of any issue in running 200 MHz at room temperature. You may want to try the following PLL setting to get 200 MHz from 16 MHz OSC.

PLL1= 0x21036300, PLL2 =0.

Thanks and regards,

Zhaohong

0 ALLEN POETZSCH over 13 years ago in reply to Zhaohong Zhang

Prodigy 245 points

The setting you gave me seem to work OK at 200MHz. I would like to know how these corolate with HalcoGen settings.

0 Zhaohong Zhang over 13 years ago in reply to ALLEN POETZSCH

TI__Mastermind 22715 points

Allen,

You can check the oscillator and pll section of TRM to see the impact of differences of the two settings. One thing to remember. The PLL VCO frequency is limited about 550 MHz.

Thanks and regards,

Zhaohong

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EMIF Asynchronous speed