DMA

For formation of short signals on an output of port of general purpose I used the DMA module in a mode of block transmission. Serial transmission of data array to port was made for testing of working capacity { 0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1 }. The following pattern was as a result watched approximately:



to what appearance of time delays between transmission of 4 words can be connected?

DMA module initialization:

DMA_GR1_ARRAY[16] = { 0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1 };

void DMA_Packet_Init(void)
{
    TDMA dmast;
    dmast.chan = 13;         
    dmast.reqline = 13;
    dmast.lnf = 1;
    dmast.lnb = 16;
    dmast.src = (unsigned long)DMA_GR1_ARRAY;
    dmast.dst = (unsigned long)&gioPORTA->DOUT;
    dmast.chain = 0;
    dmast.addmr =  ADDR_INC1;
    dmast.addmw  = ADDR_FIXED;
    dmast.ttype = BLOCK_TRANSFER;
    dmast.eioff_dst = 0;
    dmast.eioff_src = 0;
    dmast.fioff_dst = 0;
    dmast.fioff_src = 0;
    dmast.prio = 1;
    DMA_Init(&dmast);
}



void DMA_Init(TDMA * dma)
{
    register uint32_t i=0,j=0;
    dmaReqAssign(dma->chan,dma->reqline);
    dmaRAMREG->PCP[dma->chan].ISADDR  =  dma->src;    // src    
    dmaRAMREG->PCP[dma->chan].IDADDR  =  dma->dst;     // dst
    dmaRAMREG->PCP[dma->chan].ITCOUNT =  ((dma->lnf) << 16) | dma->lnb;    
    dmaRAMREG->PCP[dma->chan].CHCTRL  = (ACCESS_32_BIT  << 14)|
                                        (ACCESS_32_BIT  << 12)|
                                        ((dma->ttype) << 8 )|
                                        ((dma->addmr) << 3 )| // src
                                        ((dma->addmw) << 1 )| // dst
                                        (AUTOINIT_OFF);
    dmaRAMREG->PCP[dma->chan].CHCTRL |= ((dma->chain) << 16);
    dmaRAMREG->PCP[dma->chan].EIOFF   = ((dma->eioff_dst) << 16) | (dma->eioff_src);
    dmaRAMREG->PCP[dma->chan].FIOFF   = ((dma->fioff_dst) << 16) | (dma->fioff_src);
    i = (dma->chan) >> 3;                /* Find the register to write                  */
    j = (dma->chan) -(i << 3);           /* Find the offset of the 4th bit              */
    j = 7 -j;                            /* Reverse the order of the 4th bit offset     */
    j = j<<2;                            /* Find the bit location of the 4th bit to write*/
    dmaREG->PAR[i] &= ~(0xf<<j);
    dmaREG->PAR[i] |= (4<<j);
    dmaREG->CHPRIOS |= (dma->prio) << (dma->chan);      //  prioritet
}