eFuse EFCERRSTAT Register Bit 5 related question

Hello Pashan,

I am checking on this and will get back with you shortly.

Hello Chuck,

That means at the end of SELFTEST sequence :

efcREG->SELF_TEST_SIGN = 0x5362F97F;

efcREG->BOUNDARY = 0x0000200F;

there will be Bit 5 of EFCERRSTAT as well as Bit 15 of EFCPINS will be SET together.

Is the correcct assumption?

Thank you.

Regards

Pashan

Hello Pashan,

Yes, your assumptions are correct.

Hello Chuck,

Can you please provide me an example eFuse Self Test code where both the bits are set?

Something similar example related to CRC from Test Team posted by Prathap at the following link :

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/219629.aspx

Posted by Prathap  on Oct 17, 2012 7:24 AM

I assume that you mean  Bit 5 of EFCERRSTAT as well as Bit 15 of EFCPINS when you reference "both bits" being set?

If this is the question, you can execute the start up code provided in SPNA106a.zip with a break point at the line

if(!(efcREG->PINS & EFC_SELF_TEST_ERROR) & !(efcREG->ERROR & SELF_TEST_ERROR))

in the function checkEFCSelfTest(void).

Once the breakpoint is reached you can view the register contents to verify.

Note that bit 5 of EFCERRSTAT is primarily there for production and debug purposes and isn't needed in the application. If the instructions associated with the self test do not complete properly, an error will get generated and indicated in the self test status register.

Hello Chuck,

I did the test and I don't see Bit 5 of ERRSTATUS Register being SET at all.

Bit 15 of EFCPINS Register is SET.

Let me know.

Thank you.

Regards

Pashan

Hello Pashan,

Thanks for the feedback. Perhaps there is something wrong with my understanding of this bit. I have asked one of the eFuse controller IP experts to have a look at this register and provide me with some feedback. I will get back with you when I get this clarification.