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When does Bit 15 of EFCPINS register in eFuse gets cleared?

Pashan None
Genius 5660 points


Hello Support,

Please let me know under which condition the Bit 15 of EFCPINS register within eFuse can be cleared at the end of eFuse Self Test RUN.

Please relate to the SYSESR Bit related various RESET Conditions like WDRST, EXTRST, OSCRST, SWRST, MPMODE, CPURST, PORRST for clearing the Bit 15 of EFCPINS Register.

I am assuming the BIT is not R/WC but only READ_ONLY type.

Thank you.

Regards

Pashan

 

  • 0
    TI__Guru 59540 points

    Hello Pashan,

    The Bit 15 (EFS SelfTest Done bit) of the EFCPINS register is set to a 1 upon completion of the eFuse self test. It is cleared to 0 upon a nPORRST and the other reset sources will not clear it. It will also be cleared to a 0 when another self test is initiated.