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Question about MibSPI1 Multibuffer RAM in TMS570LS0432 device

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS0432, HALCOGEN

Hello Support,

I asume all the cells in the MibSPI1 Multibuffer RAM are Read/Write.

I am using TMS570LS0432 device and if I write 0xFFFF_FFFF at address 0xFF0E_0000,

I get back 0xFF0F_FFFF while reading back the same location.

This is valid for all MibSPI1 RAM Locations.

Can you please verify if it is a BUG in the Silicon or my understanding is incorrect?

Thank you.

Regards

Pashan

 

  • 0
    TI__Guru 59540 points

    Hello Pashan,

    Bits 20-23 of the MibSPI RAM buffer are not writable in the LS0432 device because there are only 4 CS pins available for MibSPI1 on the device. This is noted in the CSNR description in table 21-45.

  • 0 in reply to Chuck Davenport
    Genius 3950 points

    Hi Chuck D.,

    I posted these questions on a old thread but didn't receive any feedback, so I guess I can continue this one since it is talking about almost the same thing, except the PN of the MCU but within the same family.

    I need your help on the MibSPI chip-select allocation on the TMS570LS2134PGE package.

    I need to use the MibSPI1 and MibSPI3 in multi-buffer mode. On page 1332 of the spnu499a TRM, for CSNR field, it states on Note 2 that "Bits [23:20] is not writable in the device due to non availability of Chip select pins CS[4:7]", while on page 16 of the spns165a datasheet, for instance in the 144PGE package, MIBSPI1NCS[4] and MIBSPI1NCS[5] are shared with N2HET1[15] and N2HET1[24] respectively.

    My questions are:

    Can one configure those shared pins to use as MibSPI chip-select?

    If so, which register need to be configured to select the pins for one device rather than for the other?

    Otherwise, what is the purpose to list those pins in the datasheet?

    Many thanks!

  • 0 in reply to Chuck Wong
    TI__Guru 59540 points

    Hello Chuck W.,

    The original question in this thread was for the TMS570LS0432PZ which is a 100 pin packaged device. For this device we only utilize 4 CS's in the MibSPI implementation which is why there is a limitation for it (See SPNS186a). Fot the TMS570LS2134PGE, as mentioned in it's applicable datasheet, CS4 and CS5 are available but muxed behind the N2HET1 pins you mentioned in your post. To select the alternate function on these pins, you would need to select the alternate pin functions using the IOMM module. This can be done by following the procedures outlined in the TRM (SPNU499b chapter 4) or by using Halcogen to configure the desired output pin fucntions.

  • 0 in reply to Chuck Davenport
    Genius 3950 points

    Hey Chuck D.,

    I appreciate very much your quick reply. As we are looking forward for the schematics finalization and PCB layout. Thank you.

    So my understanding is that the Note 2 on is somehow inaccurate on page 1332 of the spnu499a TRM, for CSNR field, which states that "Bits [23:20] is not writable in the device due to non availability of Chip select pins CS[4:7]".

    Am I correct to assume this?

    Also there is a typo on the first column of this field: the bit field should be "23-16" and not "32-16".

    Thanks again!

  • 0 in reply to Chuck Wong
    TI__Guru 59540 points

    Chuck W.

    It would appear that this is an inaccuracy in the TRM regarding the note but I would like to get confirmation from the document owner before confirming it as a typo. I will ask the document owner to address your concerns in this thread.

  • 0 in reply to Chuck Davenport
    Genius 3950 points

    Thanks Chuck D,

    Do you have any news from your colleague?

    Regards.

  • 0 in reply to Chuck Wong
    TI__Guru 59540 points

    Chuck W.

    I have confirmed with the document owner that this note should not be included in the TRM for the LS2134 device. I will submit a document feedback request to have it removed and correct the typo in the bit numbers column.

  • 0 in reply to Chuck Davenport
    Genius 3950 points

    Chuck D.,

    You have a great weekend!

    Thanks again!