Hi Ti Gurus,
I've got a TMS570LS20216 which I've configured to successfully send and receive data. Polling and interrupt mode works.
Is there a way for the Ti chip to send a break signal on the UART line?
Cheers,
Jude.
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Hi Ti Gurus,
I've got a TMS570LS20216 which I've configured to successfully send and receive data. Polling and interrupt mode works.
Is there a way for the Ti chip to send a break signal on the UART line?
Cheers,
Jude.
Jude,
See if this is what you are looking for: (Section 13.3.4.1 in case the copy is not clear enough)
13.3.4.1 Idle-Line Multiprocessor Modes
In Idle-line multiprocessor mode, a frame that is preceded by an idle period (10 or more idle bits) is an address frame. A frame that is preceded by fewer than 10 idle bits is a data frame.
There are two ways to transmit an address frame using idle-line mode:
Method 1:I n software, deliberately leave an idle period between the transmission of the last data frame of the previous block and the address frame of the new block.
Method 2: Configure the SCI to automatically send an idle period between the last data frame of the previous block and the address frame of the new block. Although Method 1 is only accomplished by a delay loop in software, Method 2 can be implemented by using the transmit buffer and the TXWAKE bit in the following manner:
Step1 : Write a 1 to the TXWAKE bit.
Step2 : Write a dummy data value to the SCITD register. This triggers the SCI to begin the idle period as soon as the transmitter shift register is empty.
Step3 : Wait for the SCI to clear the TXWAKE flag.
Step4 : Write the address value to SCITD.
Kevin,
I think it might work. Just need to get my way around it I guess.
The reason I was after the break detect in the first place was to trigger a DMA receive upon a "created" break. So typically, the sender would issue a break and follow that by data which the DMA would receive and interrupt the CPU after the DMA buffer is full.
How would I use the idle-mode to do this? Can the idle phase give me the interrupt which the DMA can rely upon to trigger?
Jude,
If you are trying to detect a BREAK, why not directly use the BREAK DETECT interrupt?
Or if your ultimate goal is to use the DMA to transfer received data, set the RX DMA bit (by writing a 1 to SET RX DMA). This will send a DMA request signal when the receive data is ready. You can configure the DMA to interrupt the CPU after some number of transfers...
Best Regards,
Forum Support
Kevin,
The issue I was trying to get at was to _create_ a deliberate break, detecting the break wouldn't be an issue. Having said that, your suggested approach to the DMA sounds like the way I need to approach the setup I've got. I'll go and give that a try.
Cheers,
Jude.