Hi,
I am using the XRM48L952ZWTT part and interfacing to a FPGA using a memory mapped interface.
For the HW I have followed the the guide in the TRM for a 16 bit EMIF interface and thus am using ADD(6 to 0) and BA1 to generate an 8 bit address. The data bus is 16 bits wide.
When I run the code I notice that the bottom 3 bits of the address (ADD1, ADD0, BA1) are stuck at zero. Therefore only every 8th register in the FPGA memory map is accessed. What is the problem with the EMIF setup? and what so I need to do to fix it?
As far as I can tell processor read and write cycles seem to work, it is only the address that is wrong.
The EMIF_CLK is set to 20MHz.
Thanks for any help.
Best wishes
Peter
