Where can I find CPU DMA Bus Arbitration mechanism description in TRM spnu499.pdf

This info is documented in the ARM website:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0363g/Cbbcffhd.html

In general as mentioned above the the order is LSU, PFU and then AXI slave and in general it is a fixed priority algorithm.

However, I am reasonably certain that they eventually timeout and give priority to the AXI slave request. I need to investigate further to determine the number of CPU cycles after which they timeout.

Pashan, Based on some simulation observations I see that once in 16 cycles CPU will give a slot to the DMA request. Each response phase of a burst from DMA though would be responded to once in 16 cycles. Of course this is assuming that the CPU is requesting code/data on flash interface all the time which is not frequent. If CPU were to give an idle cycle in between the DMA would surely receive a slot.

Hello Abhishek,

Thank you for the simulation result.

Now I have the next question.

After every 16 GCLK, DMA will get a chance. Now suppose DMA Transfer Count size is 8K of 64-Bit Block.

Does it mean that CPU will not get a chance to execute from the same Flash Space until and unless that particular large BLOCK of DMA Transfer is completed?

Thank you.

Regards

Pashan

Pashan, Perhaps I wasn't clear. The CPU grants the DMA access a cycle for every 16 cycles. In those 16 cycles if the CPU needed the bus it will use it. Now if there is an 8K transfer you have 1K data phases. Hypothetically if the CPU were executing from the flash all this time, it will take 16K cycles to finish this transfer. Now in reality there will be some idle cycles as and when the CPU is waiting for some other data so practically speaking the transfer will finish much sooner.

Hello Abhishek,

Things are becoming clear.

So, CPU performs temporary yield of the BUS Control to DMA for every 16 GCLK if needed by DMA.

Also DMA can no way grab more BUS cycles contiguously when CPU needs BUS clock cycles, even though DMA has a large block to transfer using the BUS Clock.

Are all the above statements correct?

Thank you.

Regards

Pashan