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TMS570 - clock setting

Jiri Janacek
Genius 3315 points

Other Parts Discussed in Thread: HALCOGEN

Dear TI support,

just minor remark - in the TMS570LS31x  TRM (spnu499.pdf)  on the page 177 there is following note regarding CLNCNTL (@ 0xFFFF FFD0) register:

The application must configure the VCLK2 ratio, read back the contents of the CLKCNTL register, and then configure the VCLK ratio.

Contrary to that source code (system.c) generated by HalCoGen includes "simple" setting of clock dividers without a read back. Well, this code is working properly ;-)

/** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */
systemREG1->VCLKR = 1U;
systemREG1->VCLK2R = 1U;
systemREG2->VCLK3R = 1U;

Please, may you clarify me what is beyond the note, is that obligatory and missed in this case or is just optional?

Many thanks in advance,

Best regards, Jiri

  • 0
    TI__Mastermind 22375 points

    Jiri,

    The way Halcogen takes care of the clock initialization is correct.

    It is important to set VCLK and VCLK2 with a delay in between the 2 write access to the system control register, as it is done with Halcogen.
    systemREG1->VCLKR = 1U;
    systemREG1->VCLK2R = 1U;

    VCLK and VCLK2 cannot be set at the same time.

    I hope this clarify your question.

  • 0 in reply to Jean-Marc Mifsud
    Genius 3315 points

    Hi Jean-Marc,

    thanks for your clarification / confirmation!

    However, I think that following C-code also leads to 2 write accesses in a bit different time - that is in accordance with the note within the TMS570 TRM, is not? :

    systemREG1->VCLKR = systemREG1->VCLK2R = 1U;

    Assembler produces by CGT compiler:

    .dwpsn file "../system.c",line 220,column 5,is_stmt
    MVN A2, #47 ; |220|
    LDR A1, [A2, #0] ; |220|
    MOV V9, #1 ; |220|
    BIC A1, A1, #251658240 ; |220|
    ORR A1, A1, V9, LSL #24 ; |220|
    STR A1, [A2, #0] ; |220|
    MVN A2, #47 ; |220|
    LDR A1, [A2, #0] ; |220|
    BFI A1, V9, #16, #4 ; |220|
    STR A1, [A2, #0] ; |220|

    In other word, is it possible to to set VCLK and VCKL2 in "the same time" somehow? Is that case a code sequence where one asm STORE is immediatelly followed by another STORE instruction?

    Many thanks in advance,

    Best regards, Jiri

  • 0 in reply to Jiri Janacek
    Genius 3315 points

    Extension of previous post:

    Why not, in ASM code it might happen ;-)

    Anyway as you mentioned "It is important to set VCLK and VCLK2 with a delay in between the 2 write access to the system control register" - this rule is given by some propagation time of dividers / counters (D latches?) ?

    Thanks,

    Jiri

  • 0 in reply to Jiri Janacek
    TI__Mastermind 22375 points

    Jiri,

    By looking to the assembly code, your syntax is correct.
    2 store are performed to set the 2 prescaler, and yes there is a delay in between, so the requirement is fulfilled.

    This requirement applies when the 2 prescaler VCLK and VCLK2 are changed from their previous value.

  • 0 in reply to Jean-Marc Mifsud
    Genius 3315 points

    Hello Jean-Marc,

    Yes, the assembly code should be right - it has been generated by TI Assembler ;-)

    Thanks for Your hints,

    Best regards, Jiri