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TMS570 Clock tree - ADC, nHET, EMIF

Jiri Janacek
Genius 3315 points
Other Parts Discussed in Thread: HALCOGEN, TMS570LS3137

Dear all,

I have found many various values of all internal frequency within E2E forum as well as in available documentation (datasheet and TRM).  So I would like to ask you for clarification.

I am mainly interested in following values (name convention used in HalCoGen as well as within most of documents I guess):

1) ADCs supplied by VCLK1

2) NHETs supplied by VCLK2

3) EMIF supplied by VCLK3

Theoretically, a limit of all above mentioned "clock branches" is 100 MHz. If we consider GCLK=180 MHz (TMS570LS3137 ZWT device) and apply VCLKx Divider=1, then a real maximum frequency of all three clocks is 90 MHz, is not?

Ad 1) The datasheet (spns162a) says: Total Sample/Hold/Convert time: 600ns Typical Minimum at 30MHz ADCLK

So I assume that maximum VCLK1=30MHz --> well, it is enough high freq for all other peripherals connected to VCLK1.

Ad 2) Two NHET instructions (means following factors hr = 1, lr = 2, does not?) should be enough to generate simplest PWM signal (continuous clock), right?

HRP = hr / VCLK2 = {1 / (80 MHz)} us

LRP = HRP * lr = {2 / (80 MHz)} us (= time of one logical high or low level)

Does it means that maximum PWM output has 20 MHz (total period of logical high and low)? 

Ad 3) Is then a maximum throughtput (100 MHz * 16 bits)? 

Thanks in advance,

Cheers, Jiri

  • 0
    TI__Mastermind 22715 points

    Jiri,

    Assume that in your system, VCLK1=VCLK2=VCLK3=90MHz.

    (1) There is a clock divider in ADC module which derives ADCLK from VCLK1.

    (2) NHET runs from VCLK2. You can set HR equal to VCLK2. The LRP depends on the number of NHET instructions needed to perform the timer function. If you need to run up to 32 instructions, LRP will be 32xVCLK2.

    (3) EMIF throughput is limited by the sum of two factors. One is the timing at the memory interface. The second one is the internal delay. The maximum burst size for EMIF is 8x16bit. When the R4 MPU is configured as stronly ordered form the external memory space, there is a 12 VCLK1 cycles internal delay for each burst read or write. Single 16 bit read/write can be considered as burst size of 1. The internal delay for write is reduced to 2 VCLK1 cycles when R4MPU for this region is configured as device.

    Please let me know if this answers your question.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Hi Zhaohong,

    thanks for your reply!

    May I submit further questions / comments:

    Ad (1)  

    For next lines please consider Prathap's answer in the thread http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/58734.aspx

     I think the clock divider you mentioned corresponds with PS value (ADCLK PRESCALE SELECT). In the above link there is stated: min PS = 1 - OK, it might be feasible on some devices - not the current case. If we now consider VCLK1=90MHz, then minimum value of PS = 2  according to a formula fADCLK = fVCLK / (PS + 1). It is in accordance with maximum ADCLK = 30 MHz defined in spns162a datasheet (page 118) tcADCLKmin=0.033us. 

    Well, a table on this page contains futher important value ;-) - S/H/C total time = 0.6us

    Based on Prathap's formula TTOTAL = CHN * TCHANNEL + (CHN-1) * 5 *TVCLK 

    for ADC1 24-channels it gives TTOTAL = 24 * 0.6us + (24-1) * 5 *1/90MHz = 15.67us ---> maximum sampling frequency of measured signals is 63.7kHz (OK, considering Nyquist theorem maximum signal freq is cca 30kHz)

    May you confirm this calculation?

    Thanks in advance,

    Cheers, Jiri 


  • 0 in reply to Jiri Janacek
    Genius 3315 points

    Hello,

    slight correction:

    according to a post (attached 3250.AWM_timings.docx) of this forum thread the delay (called Tscan, I guess) between End-of-Conversion of  a channel and Start-of-Conversion of next channel (they both belong to the same group) is 4 VCLK1 cycles, not 5 cycles as described above.

    I am a bit surprised that "channel switching" delay is not described by an amount of ADCLK cycles. Does it mean that the delay Tscan is always equal to 4 VCLK1 cycles regardless a value of prescaler PS (or ADCLK frequency in other words)?

    Thanks in advance,

    Jiri

  • 0 in reply to Jiri Janacek
    TI__Mastermind 22715 points

    Jiri,

    There are two steps in A/D conversion for a channel; (1) sample and hold (S/H), and conversion. Most of the time is taken by conversion. For the on-chip A/D converter, The connection to the input mux is disconnected after the conversion is started. Since the input mux can be switched to next channel during the the conversion of the current channel, "channel switching "delay does need to be taken into timing calculations. The delay between the end of conversion to the beginning of next conversion in the same group is fixed at 4 VCLK1 clocks regardless of ADCLK setting.

    Please let me know if this answers your question.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Hello Zhaohong,


     thanks for your confirmation of the amount of VCLK1 cycles between conversions. I am satisfied with this clear statement, however I am still wondering why this delay does not depend on ADC internal clock ADCLK? ;-) I would assume that channel switching is synchronized by ADC clock and not by "external" peripherals (in point of ADC view) clock.

    Yes, according to the TMS570LS3137 datasheet spns162a S/H delay = 0.2us, conversion delay = 0.4us for 12bit mode.

    Frankly, I do not understand why should the channel switching  need to be taken into timing calculations when it is performed in parallel to the conversion of the last channel. Obviously, channel switching takes a few tens of nanoseconds in comparison to hundreds of nanosecons, does not?

    I agree that this issue (delay of channel switching) is not really important (as described in the previous sentence) in final time conditions... anyway I would like to ask you for clarification.

    Many thanks in advance,

    Cheers, Jiri

  • 0 in reply to Jiri Janacek
    Genius 3315 points

    Zhaohong,

    may you clarify previous statement: "Since the input mux can be switched to next channel during the the conversion of the current channel, "channel switching "delay does need to be taken into timing calculations."

    As I mentioned in the last post, I would have expected opposite conclusion: "channel switching "delay does NOT need to be taken into timing calculations.

    Thanks in advance,

    cheers, Jiri

  • 0 in reply to Jiri Janacek
    TI__Mastermind 22715 points

    Jiri,

    Thanks for pointing out the typo in my reply. I meant to say that "channel switching "delay does not need to be taken into timing calculations.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Hello Zhaohong,

    thanks for your confirmation!

     I am trying to summarize explicitly these information - the originally mentioned formula

     TTOTAL = CHN * TCHANNEL + (CHN-1) * 5 *TVCLK

    has been already modified during our discussion - channel switching takes 4 cycles 

     TTOTAL = CHN * TCHANNEL + (CHN-1) * 4 *TVCLK 

    but final shape should be as follows (channel switching has been finished before channel conversion is complete)

    TTOTAL = CHN * TCHANNEL

    Thanks for your support and hints!

    Cheers, Jiri