DMA buffer configuration

hi,

Thanks for the response.

I might need some more suggestions on the points below.

1. My application should copy the data present in SCIRX buffer[SCI buffer is filled with continuous stream of bytes] and load the data into the destination buffer created in RAM.
2. I m unaware of the number of bytes I ll be receiving hence i cant allocate fixed number of bytes to my destination buffer. Due to memory constraints I cant provide a large buffer, So I ll have to go with, say 50 bytes max.
3. Whenever i read the destination buffer it should provide me the latest 50 bytes of data and there should not be any data loss. So i want my destination buffer to be a circular buffer.
4. What can the DMA configurations be so as to satisfy the above requirements?

And to add to this. i tried hardware triggering using the configurations i shared before by making following changes

•  In SCI i enabled the SCI RX DMA(bit 17 of  SCI Set Interrupt Register)
• Addressing mode read as Constant.

With these settings i was unable to read the data from SCIRX buffer.

Thanks and Regards

pallavi

Zhaohong,

Thank you very much for the quick response.

Isn't there any other way other than using interrupts? Application doesn't allow us to use interrupts.

Please let me know what could be done if i go for polling mode instead of interrupts.

Thanks and regards

Pallavi

Hi Zhaohong,

I am working with Pallavi on this project, thank you very much for all your help.

I don't think that the use of interrupts is necessary for us. I assume you suggested that so we know when there are 50 bytes available and so should perform the read of the destination buffer.

In fact we will be polling for new data at a fixed time period and what we need is to read anything received via the SCI interface since the last read. We will set the size of the destination buffer to be about twice the size of the amount we would expect to receive in the given period. So initially we know the DMA engine will begin populating the destination buffer at the first location and the first time we need to read we request the current destination address from the DMA engine. We read from the initial destination address to the current destination address and then store the current destination address. Next time we use the stored value as our starting point in the destination buffer and again request the current destination address from the DMA engine and so it continues. As you say, with auto initialisation enabled and with DMA requests being generated by the SCI module each time a frame of data is available for transfer, the data will be transferred until the defined block size has been transferred and then automatically reset the destination address to the start of the buffer.

The only concern I have is retrieving the current destination address from the DMA module. I have read on another thread on this forum that the CDADDR in the working control packet is only updated when an arbitration between DMA channels occurs, so with only a single DMA channel enabled we may not be able to use this to find the real current destination address. From other forum postings on this subject I believe that the destination address for the current active block is held in PBACDADDR so this could be used to get hold of the current destination. However, in some cases our application requires 2 DMA channels to be simulaneously running and as pointed out in the other thread I have read on this subject if we were to use DMASTAT register to determine the current active channel and then read PBACDADDR if the channel we needed was currently active, there is a small but real chance that an arbitration could have occurred by the time we read the value in PBACDADDR.

I have considered the possibility of reading DMASTAT before and after the read of PBACDADDR on the assumption that if the active channel is unchanged from one read to the next that there has not been an arbitration, but we wondered if there was a less clunky solution to this problem.

Thanks,

Mark.

Mark,

A DMA channel is switched out of the queue when there is no pending transfer. The addresses in the working control packet always reflect the addresses of the last completed transfer.

Thanks and regards,

Zhaohong

Hi Zhaohong,

The behaviour you describe is what we had hoped and would mean our application will behave as expected.

In this case though, could you please explain what is being described in the following thread?

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/158061.aspx

Thanks,.

Mark. 

Mark,

I took a look at this thread you referred. In order to make the address in working control packet updated after transferring one byte from SCI, you need to set up the following.

(1) There is only one element in a frame. the element size is 8 bit.

(2) The trigger to DMA is set for frame transfer.

(3) Enable DMA on SCI module

SCI will generate a DMA request after receiving a byte. This request triggers a DMA frame transfer from SCI RX buffer to system RAM.  The address in the working packet is updated after the completion of frame transfer.

Thanks and regards,

Zhaohong