DCAN Busy Bit for IF1 and IF2 Interface are seprate bits or same bit for both the RAM IFx Registers?

Pashan None

Hello Support,

There is a BUSY Bit in IF1CMD as well as IF2CMD registers.

Are they separate hardware bits or same for both IF1CMD and IF2CMD registers?

Reason being, when IF1CMD Busy Bit is SET, do I expect to see IF2CMD BUSY Bit also SET or they are independent of each other?

Is it possible to write to IF2CMD Register when IF1CMD register BUSY Bit is already SET?

Thank you.

Regards

Pashan

over 13 years ago

0 Zhaohong Zhang over 13 years ago

TI__Mastermind 22715 points

Pashan,

This BUSY bit indicates that a data transfer between the interface registers and DCAN message RAM is in progress. IF1 and IF2 and independent to each other.

Thanks and regards,

Zhaohong

0 Fabian Nenniger1 over 13 years ago in reply to Zhaohong Zhang

Prodigy 185 points

You mentioned that IF1 and IF2 registers are independent. What happens when I try to access the same message number in RAM concurrently, using these two different interfaces?

Regards Fabian

0 Zhaohong Zhang over 13 years ago in reply to Fabian Nenniger1

TI__Mastermind 22715 points

Fabian,

I could not see how you can access the mailbox "concurrently" because you should poll the status bit to wait the transfer between the IF registers and mailbox is complete.

Thanks and regards,

Zhaohong

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DCAN Busy Bit for IF1 and IF2 Interface are seprate bits or same bit for both the RAM IFx Registers?