Gurpreet,

You can use the Stellaris ICDI interface with IAR.  If you go to Project->Options->Debugger, under Driver, select TI Stellaris, then click OK.

You can do profiling with IAR.  I found this link from IAR that you may find very helpful.  You will need a J-Link/J-Trace to do function profiling with IAR.  If using CCS, this wiki page describes how to do function profiling: http://processors.wiki.ti.com/index.php/Profiler. 

-Rebecca

Rebacca,

Thanks for reply,

Do I need to purchase separate J-Link/J-Trace(Hardware) to do Function Profile with IAR ?

or only LM4F232H5QD Evaluation Board is enough for that?

Also for CSS a have check this link http://processors.wiki.ti.com/index.php/Profiler.

Profiling Solutions for Stellaris CortexM3/M4F Targets

The function profiler is not supported on Stellaris hardware. A solution to obtain profile data is described in this wiki article: Watchpoints for Stellaris in CCS.

--

Gurpreet

Gurpreet,

You will need to perform separate IAR hardware in order to do trace (function profiling) on a Stellaris device.

You are correct.  Function profiling is supported in the Cortex M3 core simulator included with CCS v4/v5, just not with the Stellaris hardware. You can instead use a count event, an alternative method suggested by CCS (wiki found here).

-Rebecca

Rebecca,

I am able to use a count event, an alternative method suggested by CCS.

But How Can I associate count event no. (say 20) in no. of microseconds with lm4f232h5qd evaluation board?

Thanks

--

Gurpreet

Rebecca

Thanks for reply...I have successfully build code with CCS .

But, When I am trying to Debug code on EK-LM4F232 board, the code reaches at FaultISR() Function.

How can I find out problem?

Also, My Code contains large no. of array of and structure. To reach at FaultISR() i think due of small size of stack i have go through on some Forums.

How can i increase the size of stack in startup_ccs.c ?(If problem could be because of that)

Your suggestions are welcome....

--

Gurpreet Singh

Gurpreet,

To change the stack size in CCS, go to the drop-down Project->Properities->Build->ARM Linker->Basic Options and next to "Set C system stack size", enter the desired stack size.  

This hard fault can be directly related to a stack overflow.  If increasing the stack size does not eliminate the hard fault, you may find this app note useful.  It tells you how to diagnose software faults.  There is also a section in the LM4F232H5QD data sheet called fault handling which elaborates on the conditions that can create a fault.

-Rebecca 

Hi Rebecca,

After  doing One month RnD  with ARM M4 Evaluation Board LM4F232H5QD (for educational research purpose) 

I have been using Code Composer Studio for running our code on the board. When I tried running a small code to get the cycles count

I got around 131 cycles on the CCS using the feature cycle count (an alternative method suggested by CCS (wiki found here) instead of profiling)

but when the same code is executed on IAR WORKBENCH for ARM simulator (NOT on hardware) the cycle count comes out to be around 93 cycles using its function profiler feature.

Please clarify that what could be the reason behind that.Thanks in advance..

--

Gurpreet Singh

In the attempt to lighten the load upon TI Tech Staff - especially so in the case of this ongoing - and shifting - "issue du jour"...

a) might not IAR be a superior source for the gritty details of the Kickstart version of their simulator?

b) quite often - simulator results do not fully reflect "live, in circuit test" results.  (much depends upon operational specifics)

c) could not your "research" extend into the creation of a simpler task - say the adding of two integers - and then compare CCS vs. IAR in that manner?  Gradually expand your code base to chart, "consistency" (or lack thereof) between these 2

d) "RnD" (Research and Development) really is quite well defined - taxing authorities on world-wide basis - are very, very strict as to what constitutes, "Research!"  From your writings - suspect your effort is more likely, "Design and Development" - not research.  Many, many PhDs and multi-million dollar, specialized equipment are usual in the lair of a "real" R&D firm.   Happy, continued "investigating."

Hmmm... some of us have done R&D which was mostly algorithm research...

 "RnD" (Research and Development) really is quite well defined - taxing authorities on world-wide basis - are very, very strict as to what constitutes, "Research!"  From your writings - suspect your effort is more likely, "Design and Development" - not research.  Many, many PhDs and multi-million dollar, specialized equipment are usual in the lair of a "real" R&D firm.   Happy, continued "investigating."

Our pencil and paper budget was horrendous... It was always allowed as an expense -- I have the records to prove it... ;-)

Tax department and NRC thought we were "real" -- fooled them again!

Should one wish to, "invite/signal" US IRS to your doorstep - just try and expense using category "R&D."

At 50 million USD - our firm makes no pretense to being able to perform "R&D" - at best we are D&D (design).  When we search/evaluate new techniques we are "investigating" - never researching.

Schools around the world improperly use term "research" - which degrades those who really perform such esteemed activity.  And - when time comes for serious fund injection - never/ever use "research" - VC's will quickly/none too gracefully, "run for the hills."

We did do basic research in mathematics and algorithms and had numerous yearly clean Scientific Audits and Tax Audits.

For us it was not that big an issue -- we also did up front presentations to NRC on all projects and went through the required audits there as projects were accepted, tracked and finalized.

So I know the game.

But yes people do get confused on the issues of what is research, investigation and development and R&D allowances must be carefully presented and justified. Any mistake on the language and your proposal goes into file 13 -- the green round filing cabinet on the floor.

People working in neural networks, NP (Non Polynomial Time) algorithms general networking algorithms scheduling theory and despatch algorithms and related areas still have some maneuvering room.

cheers.

Work posted - from your past - clearly had great value and I accept your assertion that it did qualify as, "Research."

That said - poster in question - this reporter - and the great "electronic/MCU focused" multitude here - will not perform nor encounter "real" research in their day to day development.  "Design and Development" - while less glamorous - is a far better descriptor - and avoids the "joy" of tax audit...