• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 1083 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RAM Trace Port - debug purpose

Jiri Janacek
Genius 3315 points


Dear all,

may the RTP module be used just as internal log memory? I do not intend to connect any external device on RTP output pins to monitor operations (data transfers) upon RAM. A dirty idea is to record RAM transfers into FIFOs included in RTC module. For this monitoring an ordinary debugger with JTAG/SWD interface (20pin connector) can be sufficient - an extended debugger with ETM (Mictor 38 pin or MIPI 60 pin) is not required then.

I think that SRAM range from 0xFFF8_3000 to 0xFFF8_3FFF belongs to RTP RAM. So my understanding is that within this memory region FIFOs are defined - 4 x 1KB, is not?

Is that feasible if RTP is configured in trace mode? A project (CCS 5.2.1.00018) is attached - a variable @0x08002000 is incremented per every second - but FIFO memory which should trace the RAM region where the variable is located is not changed as (wrongly?) expected..

5556.RTP_test.zip

Do you have any idea?

Thanks in advance,

cheers, Jiri

  • 0
    TI__Mastermind 22715 points

    Jiri,

    i have not been able to find any documents describing about the data format when viewing the FIFO in RAM test mode. There is also no information about how the RAM test mode would affect RTP functions. If you really want to do an experiment, I would suggest you only turning on the RAM test mode when viewing the FIFO.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Hi Zhaohong,

    thanks for your reply!

    So you can confirm that RTP FIFOs can be used in such a way? ;-) Please may you check a few lines within sys_main.c - is it sufficient to initialize the RTP module just by those 3 registers? If a RAM content is inspected, RTP FIFO addresses are filled by a pattern 0xC3C3C3 (alvailable background pattern of PBIST_March13N_DP) and each 4th word contains zeroes regardless of enabled/disabled PBIST for RTP dual-port RAM - seems to be a bit weird, does not?

    Sorry, I have not caught what did you mean when you spoke about "RAM test mode"?


    Thanks in advance,

    cheers, Jiri


  • 0 in reply to Jiri Janacek
    TI__Mastermind 22715 points

    Jiri,

    I am afraid that I was not clear enough in my earlier reply. I do not think that the operation you intended is feasible. First of all, there is no TI document about how the traced data is saved in the FIFO when you see them from the memory mapped address. Secondly, you can only view the FIFO from memory mapped address after you set the test bit (bit 24 of the RTP control register). Setting of this test bit enables the RAM test mode (you can read write to FIFO) . It should be turned off for normal trace operation. It means that you are not able to see the FIFO content when tracing is going on.

    It seems that you need to use some other methods.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Hi Zhaohong,

    thanks for your clear statement - obviously this is not the right way for originally planned purpose!

    As you can see in the previously attached project, this "TEST" bit 24 has been set in the code:

    rtpREG->GLBCTRL = 1<<24 | 0<<16 | 0<<12 | 0<<11 | 0<<10 | 0<<8 | 1<<7 | 1<<6 | 1<<5 | 0<<4 | 10<<0;

    However may you submit a request for some documentation regarding data format etc.  to your colleagues who are responsible for RTP module? If I understand correctly, enabling the TEST bit in rtpREG->GLBCTRL is just useful to see that something has been written (changed) into FIFO, right?

    Thanks for your explanation and support!

    Cheers, Jiri

  • 0 in reply to Jiri Janacek
    TI__Mastermind 22715 points

    Jiri,

    I have contact every person I could think of. Nobody has the information of the data format. Also, the test bit needs to be cleared in normal tracing operation. I could not visualize how it would work in real time. I would suggest looking into other ideas.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 3315 points

    Zhaohong,

    many thanks for your support - I greatly appreciate that!

    Yes, no doubt that emulators (iSystem, Lauterbach) with advanced features (supporting ETM as well as RTP) should be used...

    Cheers, Jiri