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Testing uP core errors

Marco Moreno
Intellectual 300 points


Hi,

We received some required fault testing from our 3rd party certification group and are trying to figure out how to implement them.  Essentially, we need to understand how to do the following:

1) insert fault that simulates corruption of register data in one core of the uP

2) insert fault that simulates  incorrect calculation of safety critical data processing in one core of the uP

Is it possible to inject errors in only one core of the TMS570?  It seems like we would need to disable the lock-step processing, but I don't think that's possible.  Please advise.

Thanks,

Marco

  • 0
    TI__Guru 59540 points

    Hello Marco,

    The cores in the Hercules devices are 100% lockstep and it is not possible to access only one to create the faults that you have mentioned above. As an alternative, I might suggest looking into the CCMR4 self test documentation to see if these tests will satisfy the fault testing you mention. i.e., although we cannot inject the errors directly into the cores themselves, we can create error conditions that would be coming from the cores into the CCMR4 to demonstrate system behavior in the case of a CPU fault.

    I have also copied one of our safety experts in case he might have some additional inputs/insight into the request from your third party certification group and might be able to offer information that would help mitigate their concerns.

  • 0 in reply to Chuck Davenport
    TI__Mastermind 23000 points

    Chuck has created a nice summary.  It is not possible to independently access the CPUs in the lockstep cluster, but it is possible to introduce faults in the core comparator module.

    I would be interested to see what your 3rd party group requires in terms of certification.  To date we have not seen any requests for such data but we would like to understand the reasoning to better support you in your certification effort.

    Regards,

    Karl