Hi,
I transfer Data from a TMS570LS3137 to another TMS570LS3137 via MibSPI. The Master MCU uses two Transfer Groups (TG0, TG1) to transmit Data. TG0 is configured to use three buffers and TG1 buffer length is flexible.
When I transfer data I first write Data in TG0 and TG1 (in Tx-RAM) and then trigger TG0 in software by writing TGENA bit. TG1 is triggerd by the Slave via GIO after it received data from TG0.
Because TG1 length is flexible, i transfer the length as part of the data transfered through TG0 and then configure PSTART in TGCTRL1 in the slave MCU.
It works when TG1 length is 2-125 buffers(128 - 3 buffers from TG0).
It does not work when TG1 is only 1 buffer. I figured out that the TG-ready interrupt is not generated altough PSTART in TGCTRL1 is configured to 1.
Can you figure out, what I am doing wrong here?
Kind regards,
Dominik
