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Parity RAM Area update when Parity is Disabled in the Peripheral and CPU Write to Peripheral RAM Area

Pashan None
Genius 5660 points

Hello Support,

1> For HTU DCP RAM Area, when PARITY_ENA = 0x5 [Parity Disable], I see that any change in the DCP RAM by CPU Write Action also updates the corresponding PARITY Area of DCP RAM according to the DEVCR1 configuration, even though Parity is disabled in HTU and HTU_EN=0.

2> For VIM RAM Area, when PARITY_ENA=0x5 [Parity Disable], I see that any change in the VIM RAM by CPU Write Action doesn't update the corresponding PARITY Area of VIM RAM.

Can you please confirm if this is the expected behaviour?

Also, for which Peripherals, CASE 1 above is always TRUE and for which Peripherals CASE 2 above is always TRUE for similar WRITE Action by CPU while corresponding PARITY_ENA is DISABLED state.

I couldn't find any material for CASE 1 and 2 within TRM.

Thank you.

Regards

Pashan