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fmcBus2Check function in spna106a.zip need not enable CPU ECC Detection and Correction Logic?

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS0432

Hello Support,

In the spna106a.zip example for Cortex-R4 Initialization Code, there is a function called fmcBus2Check().

Can you please confirm whether I need to enable [SET] the following bits inside Cortex-R4 core :

C9_PMCR_Register_Content -- Bit 4  -- CPU Event Export -- Enable export of the events to the event bus for an external monitoring block

C1_Auxiliary_Control_Register -- Bit 25 -- ATCMPCEN -- ATCM parity or ECC check enable

C1_Auxiliary_Control_Register -- Bit 0 -- ATCMECEN -- ATCM external error enable

for fmcBus2Check() to PASS the test of SECDED within Flash Wrapper?

Do I need to SET all the above BITS or only a few of the above bits or NONE?

Or, is it a DON'T CARE for all the above bits for fmcBus2Check() to PASS the test?

Please let me know which of the above case is valid.

Thank you.

Regards

Pashan

 

 

  • 0
    Genius 5660 points

    Hello Support,

    Also for the fmcBus2Check() to PASS the test, what must be the value if EDACMODE field within FEDACCTRL1 Register?

    Is it DON'T CARE or must be non-0x05 value?

    If non-0x05, then please explain why it is so.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    For Bus 2 access, ECC checking is a Flash wrapper function. For Bus 1 access, ECC checking is a R4 function.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhaohong,

    So for the "Bus 2 access, ECC checking is a Flash wrapper function", as mentioned by you, what shall be the value of  EDACMODE field within FEDACCTRL1 Register for the test to PASS?

    I am assuming for "Bus 2 access, ECC checking is a Flash wrapper function", Cortex-R4 side ECC Logic related and Event Export Bit related values are DON'T CARE.

    Please confirm.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    Your understanding is correct.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhaohong,

    So for the "Bus 2 access, ECC checking is a Flash wrapper function", as mentioned by you, what shall be the value of  EDACMODE field within FEDACCTRL1 Register for the test to PASS?

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    EDACMODE[3:0] = 0x5, SECDED Detection mode. In this mode, only detection is enabled. Single bit errors will not be corrected.

    EDACMODE[3:0] = all others, SECDED Correction mode. In this mode, single bit error will be corrected if SECDED is enabled.

    In detection only mode any multi-bit or single bit error will result in an ECC_MUL_ERR. Single bit error flags and profiling are disabled. The default is correction mode.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Genius 5660 points

    Hello Zhaohong,

    Attached is the EDACMODE Field definition from spnu517.pdf [TRM for TMS570LS0432 device].

    I am unable to understand the above mentioned TRM Page from your above definition in the last mail.

    Looks like TRM is talking about Bus 2 ECC Check when EDACMODE = non-0x05. Because OTP, Mirror Flash and ECC are on Bus 2 I suppose.

    In your last mail there is no mention of Bus 2 [Mirrored Flash] for EDACMODE.

    Please confirm about this discrepancy from TRM about Mirrored Flash/OTP access.

    Thank you.

    Regards

    Pashan

     

     

  • 0 in reply to Pashan None
    TI__Mastermind 22715 points

    Pashan,

    The current TRM content for the EDACMODE Field only describes the interaction between CPU and Flash wrapper for Bus 2 access.  We will add Flash wrapper operation to TRM because ECC for bus 2 is a Flash wrapper function. It works as I explained in my earlier post.

    Thank you very much for pointing out this for us.

    Thanks and regards,

    Zhaohong