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Address Parity Check for ATCM and subsequent ECC Error causes only ABORT and no ESM Group 3 Channel 7 error bit

Pashan None
Genius 5660 points

Hello Support,

After performing the following steps :

DEVCR1 contains ODD Parity

FEDACCTRL1_REG = 0x000A060A; 

FPAR_OVR = 0x00005B00;

Read Flash Area with correct ECC value

FPAR_OVR = 0x00005400;

ESM Group2 Channel 4 occurs as expected. FEDACSTATUS_REG Bit 10 is also SET.

Clear  FEDACSTATUS_REG Bit 10 and ESM Group 2 Bit 4.

-------------------------------------------------

After the above mentioned steps are performed, when CPU Read any Flash Area with ECC Error, it generates DATA ABORT but ESM GROUP 3 Bit 7 is not SET.

Any clue about this behaviour and how to override this behaviour?

Please help.

Thank you.

Regards

Pashan

 

 

  • 0
    TI__Mastermind 49120 points

    Hello Pashan,

    For each uncorrectable error detected by, or reported to the flash module, the error address is captured in the FUNC_ERR_ADD register at address 0xFFF87020. This register is then frozen from updates for other uncorrectable errors until it has been read out first. Also, this same mechanism is used to block the error signaling to the ESM module. Please read the FUNC_ERR_ADD register after clearing the flash module and ESM flags.

    Regards,

    Forum Support