• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 32 subscribers
  • Views 606 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DMA current destination address register

pallavi srinivas murthy
Prodigy 150 points

Hi

I m working on TMS570 DMA module. I have configured channel 1 for software triggering and channel 2 for hardware triggering. For software triggering, i have created two arrays, Source array that holds 50 bytes of data and destination array that has to receive the data from the source array. once the data is transmitted from source to destination(the destination array shows all the values present in source array[Tx is complete]) and the hardware triggering is performed on channel 2 and channel 2 becomes active, the Current Destination address register(0xFFF80814) must be updated with the destination address of the channel 1. this is not happening. the value at that address is 0 even after the channel arbitration. Does any of the settings need to be performed for the register to be updated?

Some information on the "DEBUG MODE" and how it affects the above situation would be helpful.

Regards

Pallavi

 

 

  • 0
    TI__Intellectual 1400 points

    Hi Pallavi,

    In order to help you get the answer quickly, I have forwarded you post to our DMA expert. He will reply you shortly.

    Thanks and regards,

    Ken Wang

  • 0 in reply to Ken Wang1
    TI__Expert 4225 points

    Hi Pallavi,

    The centralized DMA RAM fields for current transfer frame count, current element count, current src/dst address are intended for usage by the state machine to save channel context when channel arbitration occurs causing the current “incomplete” channel to be stalled.  Incomplete channels means there are remaining frames to be transferred later on.

    If the current DMA channel completes the current frame (not last frame yet) and there is no pending channel request with “higher” priority, then, there is no channel context saving.  In this case, there is no RAM update for current frame count, element count, src/dst address.

    If the current DMA channel completes last frame or block, then regardless if there is any pending channel request with higher priority or not, the current frame count, element count, src/dst address of this channel in RAM will not be updated; there is no channel context save because channel “completes” all of its frames or block.

    If there is only one channel enabled in the DMA, the channel will start and complete without any interruption from other channel.  In this case, the current frame count, element count, src/dst address of this channel in RAM will not be updated because there is no channel context saving due to no arbitration.

    To inspect the amount of transfers has been done, it is recommended to use FTC flag, HBTC flag, BTC flag or LFC flag and their associated interrupt and offset register.  It is not advise to use CURRENT values as the way to debug the DMA as it is intended for state machine context switching only.