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EMIF 8-bit/16-bit Memory Interface

Thomas Schmatz
Prodigy 80 points

It is possible to switch between the 8-bit and 16-bit mode for the same flash device? Reading some data in 16-bit mode, then reading some data in 8-bit mode.

Therefore, when interfacing to a 16-bit or 8-bit asynchronous device, the EMIF_BA[1] and EMIF_BA[0] pins provide the
least-significant bits of the halfword or byte address, respectively. Additionally, when the EMIF interfaces
to a 16-bit asynchronous device, the EMIF_BA[0] pin can serve as the upper address line EMIF_A[22]. (spn499a, page 621)

What have I to do that the EMIF_BA do not serve as the upper adress line? I want to connect the EMIF_BA[0] to the A[-1] pin of the flash device. This pin serves also as D[15] in the 16-bit mode. There would be a connection between  EMIF_D[15] and EMIF_BA[0]. Is this a problem?

Thanks and best regards,

Thomas

  • 0
    TI__Mastermind 22715 points

    Thomas,

    Would you please share why you want to dynamically switch modes? What functionality do you want to achieve? To achieve maximum throughput, you should stay in 16 bit mode all the time.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Guru 68930 points

    Thomas,

    Just to add to Zhaohong's comment.    If you have *two* devices on the EMIF,  and one is x8 while the other is x16, you only need to use a different chip select for each device.  The bus width is programmable on a per-chip-select basis -- so you can mix sizes on the same EMIF.

    Best Regards,

    Anthony

  • 0 in reply to Anthony F. Seely
    Prodigy 80 points

    Anthony,

    If it is possible to use two different flash memories on the EMIF it should be possible to use one flash in two different modes.

    Best regards, Thomas

  • 0 in reply to Thomas Schmatz
    TI__Guru 68930 points

    Thomas,

    Yes, I agree.  It's an unusual request though and this is why I think we just want to make sure we say this.   But if you have the need,  your diagram is at a high level correct.

    I think the problem with the diagram is in the choice of the AND gate to switch D15/A[-1] from address to data.    I don't think the D[15] will 3-state even if you only perform a byte write;  since we have the bus parking function to avoid letting the data lines float.

    Since you need to switch the data line, and it is bi-directional, I would consider this device http://www.ti.com/product/sn74lvc1g3157.

    It also has a low propogation delay through the switch (once the control is stable).

    Best Regards,

    Anthony