• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 32 subscribers
  • Views 317 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

EMIF signals control

Tristan Gingold
Prodigy 40 points


Hi,

according to spnu499a, 4.3.3:

• Control for other EMIF Signals:

Bit 31 of the system module control register GPREG1 at address 0xFFFFFFA0 is used to gate off the EMIF module outputs: EMIF_ADDR[0], EMIF_ADDR[1], EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8], EMIF_BA[1], EMIF_nCS[0], EMIF_nCS[3]. These 8 signals are multiplexed with NHET2 signals. By default, these terminals are tri-stated and pulled down. Any application that requires the EMIF functionality must set GPREG1[31]. This allows these 8 EMIF module outputs to be driven on to the assigned balls. 


But I don't see any mention of bit 31 in GPREG1 (2.5.1.34).

Which one is correct ?

Tristan.

  • 0
    TI__Intellectual 1480 points

    Hi Tristian,

    We are looking into this and will get back to you shortly.

     

    Hercules forum support

  • 0
    TI__Intellectual 2145 points

    Hi Tristan,

         The above clarification is correct. You should enable these EMIF terminals by setting the GPREG1[31]( system general-purpose register).Please refer to the previous post for this issue:

           http://e2e.ti.com/support/microcontrollers/hercules/f/312/p/202026/717735.aspx#717735

          Hope that this may help you.Thanks.

    Best Regards,
    Shelford

  • 0 in reply to Hari Pendurty
    TI__Intellectual 1480 points

    and below statement is true:

     Tristian,

    The statement below is true

    • Control for other EMIF Signals:

    Bit 31 of the system module control register GPREG1 at address 0xFFFFFFA0 is used to gate off the EMIF module outputs: EMIF_ADDR[0], EMIF_ADDR[1], EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8], EMIF_BA[1], EMIF_nCS[0], EMIF_nCS[3]. These 8 signals are multiplexed with NHET2 signals. By default, these terminals are tri-stated and pulled down. Any application that requires the EMIF functionality must set GPREG1[31]. This allows these 8 EMIF module outputs to be driven on to the assigned balls.

     

    We will look it why bit 31  is not relected in the GPREG1 definition.

     

    -Hecules forum support

     

  • 0 in reply to Hari Pendurty
    Prodigy 40 points

    Hi,

    thank you for the reply.  However, even with that change, I still cannot use the SDRAM on the HDK.  Do you have any sample code for it ?

    Tristan.