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Multiple DMA channels triggered with one request line

Dmitri Snejko
Intellectual 745 points


Hi,

Is it allowed to trig multiple DMA channels with one request line? I made a test and it seems work just  fine. I have two mixed up 16 bit wide data streams coming from two receive line SPI. As result the data in the buffer RAM is interleaved. To reassemble it back I made two DMA channels which are triggered  with single RX request as soon as two 16 bit words are received. Each of them is reassembling one stream and placing it in the buffer in right order. It works on a simple test program which is looping data through an SPI and repacking it back. Is there any possible pitfall then this scenario would be broken or stalls?

Regards, Dmitri.       

  • 0
    Prodigy 120 points

    Sir

               I am a student working on Some Project where I need to Sample Two Signals a a time (simultaneously) so I am using TWO ADC to sample two signals.

    Now I want to store the data in some location so I am using uDMA of SIZE 1000 so how can I use Two DMA Channels simultaneously to take the data from ADC

    and store the data. I am using STELLARIS LM3S9B92 micro controller  In this I have two Different Assignments Namely Primary (ADC0) & Secondary (ADC1) Now how to

    use uDMA such that it can pick both values. Can I have Your Code for Understanding Working of DMA.

  • 0 in reply to satish rathod
    Intellectual 745 points

    Hi Satich,

    I am not sure my code can  help you because it written for RM46, not Stellaris. They are both ARMs  but peripherals can work differently.

    The general idea is: I set up two DMA channels with two different control packets pointing the same buffer  as destination but for the second one the start address is offset by 2 . The source address is pointing the same source buffer (mibSPI RAM) but offset by 1 for the second one. Both are working with byte transfer type and there is some settings for frame/element offsets. As a request source I used a common source - SPI receive complete request. All my data is synchronous which means as soon as the request is generated all data  received and then the highest DMA channel finished its transfer all data is moved (since it has lowest priority) which syncs all transfer patterns.  I don't  know it will work in your case since your ADC should have different complete conversion time.

    Regards, Dmitri.

     

  • 0 in reply to satish rathod
    Intellectual 745 points

    Hi Satich,

    I don't see reasons why you need  to link both ADCs to one request. Even if you sample both of them simultaneously it doesn't mean they finish conversion at the same time and as soon as you don't want to check their status to sync the transfer you can't  use a single event to transfer both results. And you don't need to.

    1. Set two DMA channels (one per ADC),

    2. Set your both  ADDSSCTLs   to the same arbitration size, lets say 4 samples.

    3. In your uDMA set two channels with different control  packets (one per each ADC, for example channels 14 and  24). The control packets should be almost identical except: each of them should have different source address (ADCs fifo I believe) , the destination address should be your buffer start address for one ADC (let sat ADC0) and   the buffer start address +2 for the second one (ADC1).

    4. Set both channels arbitration size equal to ADC's,  

    5. Set both channels transfer size  (destination buffer size)/(ADCs arbitration size)/2 - 1,

    6. Set both channels request type burst,  

    7. Set both channels source address increment "No increment",

    8. Set both channels destination address increment by 32.

    9. Set both DMA channel's interrupts enabled and wait for both finished.

    This is how I see this. I did not work with Stellaris myself so you should expect there is some possible adjustments. 

    Regards, Dmitri

            

  • 0
    TI__Guru 59540 points

    Hello Dmitri,

    In general, I don't see any issues with your approach. The only caution I would give is that access to the MibSPI RAM may be gated by another master such as the CPU. If this occurs after the higher priority access and before the lower priority access, it may stall the lower priority access causing the data to be out of sequence should another RX request come in while the CPU is accessing the RAM. In short, you just need to be careful that no race conditions or latency issues are created between the masters or between the 2 DMA requests.

  • 0 in reply to satish rathod
    TI__Guru 59540 points

    Hello Satish,

    Unfortunately, I am not familiar with the IP used on the Stellaris product line other than knowing they are different than the peripherals used on the Hercules family of devices. I would suggest you reference the Stellaris E2E to see if there might be some guidance there. The Stellaris E2E can be found at the following link:

    http://e2e.ti.com/support/microcontrollers/stellaris_arm/default.aspx

     

  • 0 in reply to Chuck Davenport
    Intellectual 745 points

    Thanks Chuck,

    This is what I was thinking too. As I understand another way would be to chain two channels? How the block transfer completion interrupt would work in this case? 

    Regards, Dmitri

  • 0 in reply to Dmitri Snejko
    TI__Guru 59540 points

    Hello Dmitri,

    Block Transfer complete interrupts are channel specific so you would get a BTC interrupt for each channel. Since all BTC interrupts for a given port are routed to the same interrupt, you would observe an interrupt offset that corresponds to the primary DMA channel or the secondary DMA channel that is chained to the primary.