Hi,
I am using TMS470R1B1M. I have enabled ADIN[0] to ADIN[4], meaning I use the first 5 internal AD channels of group 1. And interrupt is enabled.
The problem is if I enable all 5 channels, the ADC0, ADC1, ADC2 are invalid data. ADC3, ADC4 OK.
If I enable first 3 channels, all 5 channels read correct data. Any other registers I missed to set?
Code is as follows:
main()
{
ADCR1 |= PS_8; // ADCLK prescaler = 8 //ADCLK:29.4912MHz/8 = 3.6864MHz
ADSAMPEV |= SEN; // ADCSAMP1 controls SW
ADSAMP1 = 24U; // SW = 24+2 ADCLK = 3.6864MHz/26 = 7.05uS
ADCR1 |= ADC_EN; // Enable ADC
ADCR2 |= G1_MODE; // Continuous Conversion
ADISR1 = 0x001F; // enable channel 0 to 4
REQMASK |= (1<<CIM_MIBADCE1); // enable channel 27 (AD1)
ADCR2 |= ENA_GP1_INT;
while ( 1)
{
if ( TRUE == AD_complete )
{
AD_complete = FALSE;
ADC0 /= 10;
ADC1 /= 10; ADC2 /= 10; ADC3 /= 10;
ADC4 /= 10;
ADC0 = 0x0000U;
ADC1=0;
ADC2=0;
ADC3 = 0x0000U;
ADC4 = 0x0000U;
ADC_count=0;
}
}
}
__irq __arm
void IRQ_Handler(void)
{
switch((0xff & IRQIVEC)-1)
{
case CIM_MIBADCE1 : // channel 27 (AD1) interrupt
ADC0 += ADDR0;
ADC1 += ADDR1; //
ADC2 += ADDR2; // y
ADC3 += ADDR3;
ADC4 += ADDR4;
ADC_count++;
if(ADC_count>=10) // use time or counter, TBD
{
ADCR1 &= ~ADC_EN;
ADCR2 &= ~ENA_GP1_INT;
AD_complete = TRUE;
}
break;
}
}
// enable group 1 interrupt at end of group 1 conversion
