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TMS570LS NHET instruction: WCAP, field: hr_lr

Chuck Wong
Genius 3950 points

Other Parts Discussed in Thread: TMS570LS20216, TMS570LS0432, HALCOGEN

Hi there,

With a VCLK2 of 128 MHz to feed the NHET, I plan to configure the NHET to sample @ 16 MHz an input frequency anywhere from 7 KHz to 12 KHz at pin 28, as follow:

  • lr = 8 cycles or up to 8 instructions, 62.5 ns per loop (16 MHz)
  • hr = 1 cycle, 7.8125 ns (128 MHz)

The NHET program would be:

  • L00 CNT { next=L01, reg=A, max=0x01FFFFFF }
  • L01 WCAP { next=L02, reg=A, pin=CC28, irq=ON, event=RISE, hr_lr=HIGH, data=0 }
  • L02 ......

With the hr_lr field enabled, given that lr=8, I can get 3 more bits (D[6..4] of Data Field) of resolution on top of the count provided by REG_A (TRM para. 18.4.3.2, Table 18-6).

My question: Is this equivalent to sampling the input frequency at 16 MHz x 2^3 = 128 MHz?

In other words: whenever the hr_lr is enabled, we sample the input signal at the VLCK2 frequency. Is this true?

Thank you for any insight.

Chuck.

  • 0
    TI__Guru 59540 points

    Hello Chuck,

    Thanks for using the E2E forum, we are looking into your question and will get back with you shortly.

  • 0 in reply to Chuck Davenport
    Genius 3950 points

    Thank you Chuck D.,

    I just want to clarify that I need to capture the free-running counter REG_A on every rising edge of the input signal and use the hr_lr feature.

    So it goes another question: is the NHET capable of using the hr_lr high resolution feature on more many pins within the same loop resolution, let say, if I have other input signals to sample using WCAP on lines L02, L03, L04 and L05 that follow?

    Regards.

     

  • 0 in reply to Chuck Wong
    TI__Expert 4225 points

    Hello Chuck,

    My name is Henry Nguyen and i am the system/apps engineers for Hercules devices.  It's nice to know you.

    Can i ask which device you are using?

    For your first question, the answer is yes.  It is equivalent to sampling an input signal at 16 MHz when HR_CLK = VCLK2 and LRP=8 in your example.  However, i would recommend that you use register R/S/T since these are 32-bit register while register A or B is only 25 bit.  You are losing HR resolution if reg A or B is used.

    For your second question, the NHET is capable of doing high resolution on each pin.  However, there is a restriction that user should only use "one" HR instruction per channel/pin.  Another word, each channel has "one" HR counter thus only one HR instruction can be supported on each channel.  But you can have multiple channels with HR instruction usage on each channel as long as your instructions do not overflow within the LRP loop.

    I hope this helps.  Please let me know if you need further clarification.

  • 0 in reply to Henry Nguyen
    Genius 3950 points

    Hi Henry,

    Thanks for your answer. For my question 2, it is clear now.

    I'm using the TMS570LS20216, I understand  that I have only registers A, B and T, all 25-bit I think. Can you confirm whether this device has the 32-bit registers R, S and T?

    As for question 1, my original question is: my LR is looping at 16 MHz (i.e. 128 MHz VCLK2, HR=1, LR=8 instructions), when using the HR resolution feature of the WCAP instruction, is this the same as sample the input signal at 128 MHz since I have 3 additional bits in the data field [D6..D4] (i.e. the loop resolution is 16 MHz x 2^(3 bits) = 128 MHz).

    Regards.

     

  • 0 in reply to Chuck Wong
    TI__Expert 4225 points

    Hi Chuck,

    I just doubled check the TMS570LS20216 part, i think this part is using NHET version which does not have an upgrade to N2HET version.

    Just a brief history:

         - TMS470M device family would have HET.

         - TMS570LS20216 family would have NHET (has improvement over HET). 

         - TMS570LS31x/21x will have N2HET (has improvement over NHET .e.g. R/S register for WCAP)

    The WCAP is enhanced in N2HET to support register S/R in addition to A/B/T. 

    When you are using HR = 1 = VCLK2, that means you are sampling input signal at VCLK2 rate. 

    Can i ask what is your minimum duty cycle on your input signal? 

    The minimum duty cycle has to be > 1*LRP in the NHET.   This is where we need to partition the LRP loop period so that the min duty cycle is > 1*LRP.

  • 0 in reply to Henry Nguyen
    Genius 3950 points

    Hi Henry,

    The worst case minimal duty cycle should be in the vicinity of 5 us (high time, I'm detecting rise2fall), take or give, so this shouldn't be a concern.

    I understand that the NHET samples input signals at 128 MHz, but just want to make sure that the recorded duration (bit D[31..4] in the data field with hr_lr turned ON will have HR resolution (in my case, ±7.825 ns or one HR cycle). Can you please confirm this?

    So TMS570LS31x/21x are newer than LS20216.

    Just a side question to help my other team that is looking for a compact MCU for a new project: other than the N2HET, does the newer LS31x/21x MCU share other peripherals architectures with the LS20216? How about the TMS470M (this is the one that they are targeting, small footprint, 100 pins)?

    Thank you!

  • 0 in reply to Chuck Wong
    TI__Expert 4225 points

    Hi Chuck,

    Let me summarize the answers as followed:

    1- WCAP instruction.  Yes, the HR field will be updated accordingly with your current setting.  I would like to clarify few things with WCAP:

             a- The high and low phase of input signal should be >1*LRP.  The period should be > 2*LRP.

             b- it is OK to have register A/B on WCAP.  Their low resolution counters are copied to the WCAP data field [31:7] when capture condition occurs.  The HR data field comes from the internal HR counter of each channel.  I was thinking of something else when i mentioned about register R/S to you.  I apologized that i may have confused you.

             c- If you just want to capture just the duty cycle, i would suggest PCNT instruction can do the job.  you can avoid the subtraction to get the duty cycle if you use WCAP instruction.  the PCNT instruction would have similar high/low phase and period requirement as mentioned in (a) above.

    2- The LS20216 datasheet (http://www.ti.com/lit/ds/spns141f/spns141f.pdf) spec that the VCLK2 frequency is max at 100 MHz.  can you please run the VCLK2 frequency to the specified number so that we can ensure the NHET behaves accordingly in all timing corners (temperature, voltage)

    3- The newer LS31x/21x share the same peripheral architectures with LS20216.  The programmer model should be identical.  We also just announced new parts with sample available now: TMS570LS04xx/03xx with 100-pin package that supports R4 (without floating point) and identical programmer model & peripheral architecture to LS31x/21x and LS20216.  The TMS570LS04xx/03xx has all the latest enhancement (e.g. N2HET, etc).  Please take a look at: http://www.ti.com/product/tms570ls0432.  i think this would be a better option for you than 470M.

  • 0 in reply to Henry Nguyen
    Genius 3950 points

    Hi Henry,

    Great stuffs that you told me, greatly appreciated.

    For 1): I get to use WCAP because I have to find the high resolution count (elapsed time) between, let say, input signal period #100 and #300. I might have been confused myself thinking on another project. Sorry.

    For 2): For some reason I missed this one. I have SPNS141C but it is still there, just specified for the VCLK instead of VCLK2, and max f_VCLK2 is f_VCLK=100 MHz.

    For 3): If there is no floating point unit, there must be an emulation library. Any figure on performance penalty by using an emulation library?

    Regards.

     

  • 0 in reply to Chuck Wong
    TI__Expert 4225 points

    Hi Chuck,

    #1 - I would like to also point out that we have a digital filter implemented on each NHET channel as well.  please look at section 18.4.6 Suppression Filter if you would like to utilize this feature on your input signal.

    #3 - Yes, the compiler will have RTS to emulate floating operation.  The penalty is hard to say because it depends on how much floating point arithmetic you have in your application.  I would recommend you to turn off FPU unit in CPU and recompile the code without (unset) -floating_support option (or don't pick any floating point option from CCS compiler option).  one way to disable FPU unit in your program (assumed you used HalcoGen to build your project) is to comment out this function: /* Enable VFP Unit */ _coreEnableVfp_();  in your sys_startup.c.  Can i ask what compiler are you using (IAR or CCS)?  If you are using CCS compiler, I would recommend you to try the 5.1 alpha release CCS compiler which has better optimization.  TI will release Beta version in a couple of weeks.  Please let me know if you are using CCS so that i can send you a link for trying out 5.1 Alpha release.

    Thanks and Best Regards,

    Henry N.
                  

  • 0 in reply to Henry Nguyen
    Genius 3950 points

    Good evening Henry,

    Thank you for the hint. I will look at the Suppression Filter.

    I'm not using HalCoGen because I have to write 100% of the code for aeroautical applications ... a certification requirement. I'm using IAR EW v6.4. I understand that you suggested me to turn OFF floating point unit support in my current application with the TMS570LS20216, in order to evaluate the difference in performance. Good idea!

    Very best regards,

    Chuck.