TMS570LS20216 DMA parity check

Hi Sunil,

I'm reading for the offset register ESMIOFFLR. DMA MPU of Group1 Channel 1 check was not enabled, only DMA Parity of Group1 Channel 2 was enabled, and the code should be 0x04 for DMA parity, I think.

Can you please confirm?

Regards.

Hi Chuck,

Yes, the code 0x4 in the ESMIOFFLR indicates a DMA RAM parity error. Can you please confirm that the DMA RAM parity check was enabled when you configured the DMA control packets? If so, then you can also read out the DMAPAR to identify the actual DMA RAM address that caused the parity error on a read.

Regards, Sunil

Hi Sunil,

Yes I enabled DMA parity check while I configured the DMA control packets, between DMAGCTRL disable and enable. But it doesn't make a difference if I enable DMA parity check only after turning on the DMA function via DMAGCTRL.

The register contents are (same everytime):

DMAPAR: ERRORADDRESS=0x1F5, EDFLAG=1

Thanks.

Sunil,

Below is my DMA initialization code:

    DMAGCTRL        = 0x00000000;           // disable all DMA functions
    DMAHWCHENAS     = 0x00008001;           // channel 0:  MibSPI1 TX (Manchester test data stream)
                                            // channel 15: and enabled for Flash CRC checking

    DMADREQASI0     = 0x01000000;           // channel 0:  request line #1 from MibSPI1 TX request
    DMADREQASI3     = 0x0000000D;           // channel 15: request line #13 from RTI event1
    DMAPAR0         = 0x70000000;           // channel 0:  use DMA Port B
    DMAPAR1         = 0x00000007;           // channel 15: use DMA Port B
    DMAPCR          = 0x0000000A;           // enable parity check

    DMACP0ISADDR    = (unsigned long) A708_TEST_MSGS;   // set of buffer address of loopback test bits array

    DMACP0IDADDR    = 0xFFF7F43C;           // MibSPI1DAT1 (fix destination)
    DMACP0ITCOUNT   = 0x000C0001;           // frame transfer=12, element transfer=1
    DMACP0CHCTRL    = 0x00005009;           // RD/WR size: 16 bits, HW triggers one block transfer
                                            // RD mode: post increment, WR mode: constant
                                            // single block transfer mode

    DMACP15ISADDR   = 0x00000000;           // set to start of Flash ROM (initial source)
    DMACP15IDADDR   = 0xFE000060;           // set to channel 1 PSA signature low (fix destination)
    DMACP15ITCOUNT  = 0x1FE00020;           // frame transfer=8160, element transfer=32
    DMACP15CHCTRL   = 0x0000F109;           // RD/WR size: 64 bits, HW triggers one block transfer
                                            // RD mode: post increment, WR mode: constant
                                            // single block transfer mode

    DMAGCTRL        = 0x00010000;           // enable all DMA functions

Thanks for helping.

Hi Sunil,

I'm really stuck now. Please help.

If I disable the use of Port B for both channel 0 and 15 by commenting out both lines of DMAPAR0 and DMAPAR1 above, no more Parity Error. However, the PEND0 and PEND15 of DMAPEND register remain remain set, which indicate that the DMA are not serviced.

DMAHWCHENAS bit 0 and bit 15 are set, indicating that both channels are enabled.

Thanks.

Hi Sunil,

I don't get it. I'm getting Parity Error on the DMA whenever request is made to the DMA controller, for both CH0 and CH15 as shown in the initialization code.

I programmed both channels of the DMA as follow:

- Destination: Fix addressing mode.

- Source: Post increment mode (source address is post-incremented by the element size).

My understanding is that the EIOFF and FIOFF registers are required only in the Indexed mode. Am I wrong?

Thanks.

Sunil,

Woowww, thank you, I think that I got it (I will try that Monday) ... but where this info is located in the manual?

So I just have to write anything to those two memory location?

Looks like this would be a better way ... if I want to initialize all DMA RAM with parity (and for other peripherals and their RAM for parity checking later on), where should I look for the procedure?

Thanks again!

Sunil,

Initializing EIOFF and FIOFF for CH0 and CH15 didn't have any effect on my problem. However, the global HW RAM initialization for DMA did the trick. :)

Best regards.

Sunil,

Is there a way to enable the parity function in a global way for selected MCU peripherals, then perform hardware RAM initialization to set parity bit, and then setup peripherals, instead of going into each peripheral to enable only the parity function, then perform hardware RAM initialization?

I'm asking this because right now, I have to split almost all peripherals initialization routines into two parts, one being called before HW RAM INIT, the other one being called after.

As a matter of fact (I reported too early in the cannot-start-target-without-JTAG-attached), I still have DCAN1 parity error if power-up without JTAG. No problem (no parity error) when start execution from the IAR EW though. I suspect that this might be related to the DCAN initialization routine being incorrectly splitted.

Thanks.

Hello Sunil,

Attached section from spnu489c.pdf is asking to enable ECC/Parity bit within Peripheral before Memory Hardware Initialization sequence in order to fill up the Parity/ECC Area.
But in your last reply, you said that it is not necessary.
Can you please confirm if TRM is wrong?

Thank you.
Regards
Pashan

Yeah, I remember that I saw something like that before, but just can remember where.

If that is the case, then all peripherals supporting Parity Check should be initialized twice, first time to turn Parity Check ON, second time all the rest.

Right now in my code, I performed HW RAM init with parity checking OFF (default), then init all devices/peripherals with parity turn ON. And so far, I don't know if I'm lucky, no error related to the parity has been observed.

Thanks to confirming that to me please.

Chuck,

Sorry for the delay. I did not realize you were waiting for additional confirmation.

When you use the auto-initialization for the DMA RAM, the associated parity bits also get initialized. This is independent of whether parity checking for DMA RAM reads is enabled or not.

Regards, Sunil

Chuck,

I was mistaken. There are four modules with associated memories which require the parity checking to be enabled in order for the parity bits to be initialized along with the data bits in the memory. These modules are: DMA, VIM, N2HET and HTU.

Sorry for the confusion that I caused.

Regards, Sunil

Sunil,

With the TMS570LS20216, I don't have the N2HET.

Can you please confirm whether this is also a requirement for the NHET module? Any other module of this MCU?

Thanks.

Sunil Oak said:

I was mistaken. There are four modules with associated memories which require the parity checking to be enabled in order for the parity bits to be initialized along with the data bits in the memory. These modules are: DMA, VIM, N2HET and HTU.

Sunil,

Just thought that you might want to know ...

From our other thread regarding how to force an "ADC parity error" and after my ESM low-level ISR was well implemented, I've discovered that the MCU modules ADC1, ADC2, DCAN1 and DCAN2 also need their respective PARITY_ENA bit set to 0xA (enable) before Global Memory HW initialization using the MINITGCR register.

Otherwise as soon as the module RAM is being used, parity errors will be generated systematically.

EDITED: As a matter of fact, I think that all RAM memories supporting the parity check function should have this bit enabled before performing Global HW Memory Initialization.

Regards,

Chuck.