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ADC trigger from HET stopped after breakpoint debugging

Yingran Duan
Prodigy 120 points


We use HET to trigger ADC conversion, and an ISR after ADC finishes conversion. Everything works fine if we let code free running.

I notice that after I set a breakpoint inside the ISR to check some values, and let it continue running again, adc stop the conversion. It seems to me that the triggering mechanism from HET get lost. The HET still running but not ADC conversion.

Why is that? How to get around with it?

  • 0
    TI__Mastermind 49120 points

    Hello,

    The ADC operating mode control register bit 24, "Continue On Suspend" (COS), defines the behavior of the ADC when the CPU is halted in debug mode. Please make sure that this bit is set in case that you want the ADC to continue normal operations even when the CPU is likely to be halted.

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 120 points

    Hi, Sunil:

    That bit IS set in our case. With furture testing it seems to me, it does not matter where I halt the program, after a few pause and run, adc stop operation.

    We used to use RTI as the trigger source of ADC, we did not experience this issue. We notice this when we wrap to HET trigger.

    Thanks,

    Yingran

  • 0 in reply to Yingran Duan
    TI__Mastermind 49120 points

    Hi Yingran,

    Can you read out the content of the ADC status register at address offset 0x88 when this issue occurs? This will indicate whether the ADC has received the trigger event or not.

    Regards,

    Sunil

  • 0 in reply to Sunil Oak
    Prodigy 120 points

    Hi, Sunil:

    Are you talking about the state machine state register (offset 0x88) or the event group status register (offset 0x6C).

    0x88 always read 0, and 6C is 1 same as event group source.

    Thanks,

    Yingran

  • 0 in reply to Yingran Duan
    TI__Mastermind 49120 points

    Hi Yingran,

    That means that the ADC is in an IDLE state as you suspected. Can you please post a snapshot of the ADC control registers in the case when you have generated the trigger condition and the ADC has missed it? Also, can you ensure that the high and low pulse widths of the N2HET signal used for triggering the ADC is at least 2 VCLK periods long?

    Regards, Sunil

  • 0 in reply to Sunil Oak
    Prodigy 120 points

    Hi, Sunil:

    This is the snapshot when unit is working fine before suspended.

    ADC stop sampling after I resume the operation. Here is the register snapshot I got when I suspend the operation.

    The HET is set to run at frequency of 20kHz, 50% duty. Here is the waveform of HET output.

    Thanks!

    Yingran

  • 0 in reply to Yingran Duan
    Prodigy 120 points

    I have this issue resolved. We use DMA module to read out the ADC value after conversion. After I change the DMA debug mode to "ignore suspend", the ADC trigger back to normal.

    Thanks to Sunil, it is your response lead me to look into the debug mode setting for relevant modules.

    Yingran

  • 0 in reply to Yingran Duan
    TI__Mastermind 49120 points

    Yingtan,

    I am glad you found the issue. I assumed that you read the conversion results by the CPU and did not inquire about it.

    Regards, Sunil