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Target Status Context Activated has encountered a problem

Richard Dualmann
Intellectual 560 points

Other Parts Discussed in Thread: MOTORWARE, RM46L852

Hi,

one project attached 5241.RM46L852SRM.zip

Compiling and Linking in CCS5.2.1 are ok.

Via USBXDSu2 emulator connected with the DRB8301-RM46-Kit in CCS5.2.1 debug mode,

Uploading this binary to flash memory, the error message is

"Target Status Context Activated has encountered a problem"

An internal error occurred during: "Target Status Context Activated".
The function "requestRegisterRead" returned an error condition (0x80070005)

sys_link.cmd is a copy from "RM46L852_instaspin_bldc" project on motorware v1.0.3.03.

How to resolve this problem? 

Thanks.

  • 0
    TI__Mastermind 22715 points

    Richard,

    I took a quick look at your project and found two errors.

    (1) In sys_invecs.asm, the entry for SWI/SVC interrupt is missed.

    (2) In the link command file, you should make sure memory sections are set to word boundary because CPU boots up in 32 bit ARM mode.. The size of the "VECTORS" section should end at 0x20 or 0x24. The start address of the "flash" section should be 024 instead of 0x22. You also need to define a ".sysmem " section for dynamic memory allocation if you use run time library functions.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 560 points

    I have changed the codes as you mentioned above in the attached file54051.RM46L852SRM.zip, but the error message appears still.

    The log is 

    CortexR4: GEL Output: Memory Map Setup for Flash @ Address 0x0CortexR4: Writing Flash @ Address 0x0 of Length 28656
    CortexR4: Using Range Mode with the following range(s): 0x0000000-0x0009FFFF,0x00400000-0x0044FFFF
    CortexR4: Erasing Flash Bank 0, Sector 0
    CortexR4: Erasing Flash Bank 0, Sector 1
    CortexR4: Erasing Flash Bank 0, Sector 2
    CortexR4: Erasing Flash Bank 0, Sector 3
    CortexR4: Erasing Flash Bank 0, Sector 4
    CortexR4: Erasing Flash Bank 0, Sector 5
    CortexR4: Erasing Flash Bank 0, Sector 6
    CortexR4: Erasing Flash Bank 0, Sector 7
    CortexR4: Erasing Flash Bank 0, Sector 8
    CortexR4: Erasing Flash Bank 0, Sector 9
    CortexR4: Erasing Flash Bank 0, Sector 10
    CortexR4: Verifying Flash @ Address 0x0 of Length 28656
    CortexR4: Finish Writing Flash @ Address 0x0 of Length 28656

    What is the problem ? 

  • 0 in reply to Richard Dualmann
    TI__Mastermind 22715 points

    Richard,

    I would suggest the following for you to debug the problem.

    Replace the instruction at address 0x0 (first in sys_invecs.asm) with " B #-8". After a power-on-reset, CPU is locked to this address. When you connect debugger to CPU, everything will be at default condition. Then you can do a "restart" to move PC to c_int00. From there you can run your code to find which function/instruction causes the problem.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 560 points

    I do not understand what you say "Replace the instruction at address 0x0 (first in sys_invecs.asm) with " B #-8"."

    Could you give me some pieces code about you mentioned above?

    Thanks.

  • 0 in reply to Richard Dualmann
    TI__Mastermind 22715 points

    Richard,

    Please see that attached file. The idea is to hold the device to default condition before CCS is connected. Then, you can insert breakpoints at steps of processing to find out which portion of the code is cause the issue.

    5344.sys_intvecs.asm

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 560 points

    Thanks.

    I will try it later.

    The TMDXRM46CNCD card has broken by accident.

     

  • 0 in reply to Richard Dualmann
    Intellectual 560 points

    After uninstall and re-install CCS 5.3.0,

    this error message disappears, up to now.

    Probably, upgrading from CCS 5.2.1 to CCS 5.3.0 online is now worked.