TMS570LS317- EMIF_nCS[3]

Livio Franchin

Hi everybody,

In one of my projects, I need to store data from TMS570LS371 on two external static RAM, using EMIF.

For this purpose, I have used two 16Mbit RAM chips : one connected to EMIF_nCS[2] and the other connected to EMIF_nCS[3].

8666.1-EXTERNAL SRAM.pdf

Since the chip connected to EMIF_nCS[3] did not work, we investigated and found out, in Silicon Errata document (DEVICE#154), that we had to write 1 to bit 31 of system module GPREG1 register. After this, the EMIF_nCS[3] did work correctly. However, now we have a new problem:

If my program writes every single address (0xaa, or 0x55) and then reads it immediately, everythings is ok:

case 1
   /* A) Fill with 0xAA */
   p = (unsigned char *)Start_Address;
   p1 = (unsigned char *)Start_Address;
   for(i=0;i<ERAM_SIZE_8bit;i++)
   {
       *p++ = 0xaa;
       if( *p1++!= 0xaa )
       {
           printf("A) Error address = 0x%x \n", p);
       }
   }
/* A) Fill with 0x55 */
   p = (unsigned char *)Start_Address;
   p1 = (unsigned char *)Start_Address;
   for(i=0;i<ERAM_SIZE_8bit;i++)
   {
       *p++ = 0x55;
       if( *p1++!= 0x55 )
       {
           printf("A) Error address = 0x%x \n", p);
       }
   }

If program writes all addresses (0xaa, or 0x55) and then reads them all, it sometimes happens, at random, the address read is not the latest but the previous one (as if the address had not been written):

case 2
   /* A) Fill with 0xAA */
   p = (unsigned char *)Start_Address;
   for(i=0;i<ERAM_SIZE_8bit;i++)
   {
       *p++ = 0xaa;
   }

   p = (unsigned char *)Start_Address;
   for( i=0;i<ERAM_SIZE_8bit;i++ )
   {
       ReadPattern = *p++;
       if( ReadPattern != 0xaa )
       {
           printf("A) Error address = 0x%x , value = 0x%x\n", p, ReadPattern);
       }
   }

/* A) Fill with 0x55 */
   p = (unsigned char *)Start_Address;
   for(i=0;i<ERAM_SIZE_8bit;i++)
   {
       *p++ = 0x55;
   }

   p = (unsigned char *)Start_Address;
   for( i=0;i<ERAM_SIZE_8bit;i++ )
   {
       ReadPattern = *p++;
       if( ReadPattern != 0x55 )
       {
           printf("A) Error address = 0x%x , value = 0x%x\n", p, ReadPattern);
       }
   }

NB: Before changing bit 31 of system module GPREG1 register, both modes (case1 and case 2) worked correctly (even if in one RAM chip only)

EMIF acces times have been set at maximun value and EMIF_CLK at 80MHz.

Can you give me a possible reason for this behavior?

Thank you and regards,

Livio

over 13 years ago

0 Zhaohong Zhang over 13 years ago

TI__Mastermind 22715 points

Livio,

According the the spec, bit 31 of the system module control register GPREG1 at address 0xFFFFFFA0 is used to gate off the EMIF module outputs: EMIF_ADDR[0], EMIF_ADDR[1], EMIF_ADDR[6], EMIF_ADDR[7], EMIF_ADDR[8], EMIF_BA[1], EMIF_nCS[0], EMIF_nCS[3]. These 8 signals are multiplexed with NHET2 signals. By default, these terminals will be tri-stated and pulled down. An application that requires the EMIF functionality must set GPREG1[31]. This allows these 8 EMIF module outputs to be driven on to the assigned balls. I do not think that any EMIF test would work if this bit is not set. Would you please double check if your EMIF tests really work when bit 31 of GPREG1 is clear?

I would suggest configuring the external memory region in device mode using R4 MPU to avoid redundant WE/OE pulses. For a single read form EMIF, it takes 24 CPU clocks internal delay (HCLK/VCLK =2) plus EMIF time. If you use LTM instruction, the internal delay is only application to first 16 bit data.

Thanks and regards,

Zhaohong

0 Livio Franchin over 13 years ago in reply to Zhaohong Zhang

Intellectual 835 points

Hi Zhaohong,

Thank you very much for your prompt response.

1) I confirm that my EMIF tests do work when bit 31 of GPREG1 is clear (obviously only on RAM chip connected to EMIF_nCS[2]).

This is very strange, as the bug also involves other EMIF signals used in testing.

2) Using R4 MPU on external memory region, the previously encountered problem [(If program writes all addresses (0xaa, or 0x55) and then reads them all, it sometimes happens, at random, that the address read is not the latest but the previous one (as if the address had not been written)] disappears. I'd like to understand the reason(s) for this, as we use two external RAM chips to store data in a safe mode according to IEC 61508 and, therefore, we must be sure that the EMIF works correctly.

For your info, it would seem that, reducing the EMIF clock from 80 to 20 MHz, the problem above also disappears, but this is too slow for our application.

3) Kindly explain what you mean by "use LTM instructions".

4) Could you please advise the timing values for correct setting of "Asynchronous 2 configuration register" when using RAM chips "R1LV1616HBG-4SI". I have set the maximum values, but I believe this is not an efficient solution.

Thanks and regards,

Livio

0 Zhaohong Zhang over 13 years ago in reply to Livio Franchin

TI__Mastermind 22715 points

Livio,

There must be something wrong. We have never see such issue on TI EVM. Would you please use a scope to check the data/address and control signals to see if they toggle between the correct levels? On this device, the max value for EMIF CLK is 66 MHz. I do think that 80MHz would cause a problem because Async RAM does not see EMIF clock. Would you please try it at 60 MHz or so to see if it helps. It seems that you are doing 8 bit read/write to EMIF. Would you please also try 32 and 16 bit read/write to see if there is any error. Since it is a 16 bit wide memory, you need to set ASIZE=1 in the A1CR register.

Thanks and regards,

Zhaohong

0 Livio Franchin over 13 years ago in reply to Zhaohong Zhang

Intellectual 835 points

Hi Zhaohong,

Here below you can find all test with different bus wide.

EMIF TEST

Access type	Test Type	MPU	EMIF CLOCK	RESULT
8 bit	write all and after read back	disabled	80 or 50 MHZ	Fail
8 bit	write all and after read back	Enabled *	80 or 50 MHZ	Ok
16 bit	write all and after read back	disabled	80 or 50 MHZ	Fail
16 bit	write all and after read back	Enabled *	80 or 50 MHZ	Ok
32 bit	write all and after read back	disabled	80 or 50 MHZ	Ok
32 bit	write all and after read back	Enabled *	80 or 50 MHZ	Ok
8 bit	write and read back	disabled	80 or 50 MHZ	Ok
8 bit	write and read back	Enabled *	80 or 50 MHZ	Ok
16 bit	write and read back	disabled	80 or 50 MHZ	Ok
16 bit	write and read back	Enabled *	80 or 50 MHZ	Ok
32 bit	write and read back	disabled	80 or 50 MHZ	Ok
32 bit	write and read back	Enabled *	80 or 50 MHZ	Ok

(*) STRONGLY ORDERED

- As you can see with MPU enabled all the test are ok also with 80MHz EMIF CLOCK.

- Sorry for previus response, but with bit 31 of GPREG1 clear all test don't work in both RAM chips.

- For our application, must be the MPU configured as STRONGLY ORDERED or DEVICE ?

Livio

0 Zhaohong Zhang over 13 years ago in reply to Livio Franchin

TI__Mastermind 22715 points

Livio,

You will have to enable R4 MPU for the EMIF region in device mode to eliminate the extra WE/OE pulses from CPU. Stronly ordered mode has the same effect. But it could hang up the CPU in some corner cases when stmia instruction is used to save data to external memory.

Performance wise, device mode provide has the best access time except that speculative fetch is not allowed. In device mode it takes CPU 12 VCLK plus EMIF time for a single read. If a ldmia instruction is used to load multitple words back to back, this 12 VCLK internal delay is only applicable to the first word. A single write only takes CPU 2 VLCK cycles because CPU just writes to its internal store buffer. If you want to move large amount of data to/from external memory, i would suggest either use DMA or use runtime library function memcpy(). Memcpy() use ldmia/stmia instructions to improve access time.

Thanks and regards,

Zhaohong

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TMS570LS317- EMIF_nCS[3]