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TMS470MF066 wakeup control register access

Other Parts Discussed in Thread: HALCOGEN

Hi there,

I’ve tried to access the Wakeup Control Registers of TMS470MF066 (located at 0xFFFFED00). I am in privileged mode and use a HALCoGen created project. In Code Composer Studio 5 the memory browser shows only zeros for these registers. When I try to write on these registers I get a bus fault.

According to the In the Gel file there is the following entry:

GEL_MapAdd(0xFFFFED00, 0, 0x00000100, 1, 1); /* Wakeup Control Register   */

I think, I should have write access, right? How Can I access these registers?

 

Thanks in advance

  • Max,

    At default, the register at 0xFFFFED00 has a value of zero and the wakeup module is in reset. You need to write a "1" to this register to release the module from reset.

    Thanks and regards,

    Zhaohong

  • Hi Zhaohong,

    I tried to write a 1 on the Wakeup Reset Control Register before. When I xor this register with 0x1, I get the already mentioned bus fault exception. In case of writing a 1 on the register, the CCS Memory Browser still shows zeroes on the register address.

    When I try to save the register values into a variable, I get a non-maskable interrupt. Please find attached the project to see what I am doing wrong.

     

    Any suggestions appreciated. Thanks.

     

    1641.TMS470M_hibernateMode.zip

  • Hello Max,

    Just wanted to touch base with you and let you know that I am looking at your project and investigating the problem. I will get back to you shortly with an answer.

  • Hello Max,

    Unfortunately, I have found that the register space you are referring to is not implemented in the device. These registers were implemented in a prior device to control some advanced wakeup features.

    For definition of wakeup sources, you will need to use the WAKEMASKSETx and WAKEMASKCLRx registers within the M3VIM module. These registers allow you to enable/disable any interrupt line that you want to wake the device from low power modes. Please see sections 8.2, 8.6.8 and 8.6.9 of the TRM for definition of enabling/disabling wakeup interrupt lines.

    I will follow through to insure the documentation of LPM wakeups are more clearly documented and remove references to the advanced wakeup registers. My apologies for the confusion.