• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 31 subscribers
  • Views 1123 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Dhrystone score

Pierre Negre
Prodigy 220 points
Other Parts Discussed in Thread: HALCOGEN

Hi, i'm playing with HDK RM48 and trying to reach the 1.66 DMIPS/MHZ score.
Several questions :
1- why does this wiki specify 450 MIPS at 270 MHz while the maximal frequency of CORTEXR4F is 220MHz?

2-  Is the code generated by Halcogen optimal? Maybe i have to specify a smaller number of flash_wait_states (Halcogen imposes 4 wait_states at 220MHz)?

3- What is the optimal configuration?
 Is this true? :
ARM’s Dhrystone measurements are made under the following conditions:
·  Dhrystone version 2.1
·  Source code: Unmodified K&R
·  Compilation modules: two
·  Inlining settings: -Onoinline option set.
·  C libraries: unmodified C libraries supplied with ADS.
·  Tool chain: ADS 1.2
·  Platform: ARMulator cycle-accurate instruction set simulator that is part of ADS.
(source)

4- Is the PMU a good way to measure such time (I managed with overflows and durations seem  representative)?

5- Without caches, I reach 1.25 DMIPS/MHZ (at 36MHz), do you think it's the maximum or i can improve things? I cannot reach that score at 220MHz, that's why I answer if I have to configure flash mode (pipeline, waitstates etc)...

6- Does the legnth of .sysmem section have an impact on performance? If so, what lenght should I impose?

7- What are the optimizations (level and for speed in CCSV5) wanted by Dhrystone Benchmark?

Thanks for your forum!
Best Regards,
Pierre.

  • 0
    TI__Expert 7650 points

    Hello Pierre,

    I will try to answer some of your questions and ask others to chime in as we go...

    1.  I'm not sure of the wikipedia source of this information.  If you look at ARM's website they characterize the R4 performance based on various optimized 65nm processes and the Artisan(tm) SC10 library and implemented as per the notes.  http://www.arm.com/products/processors/cortex-r/cortex-r4.php  RM48 safety MCU devices are specified up to 220MHz and are built in a different process, using a different library, are not cached and operate directly from flash (vs. ARM's ideal memory measurements).  In addition, we target a junction temp of 155C during design.  So, as you can see this is not an apples to apples comparison.  In fact, we are proud of  our 220MHz given the harsher environment that we design our devices to endure.  1.66 DMIPS/MHz is, of course, the ideal mark as published by ARM.

    2. I believe 4 ws at 220MHz is correct.  As a general rule, I would always advise our customers to own optimization of the code being developed even if some of it is borrowed from TI.

    3.  I will ask one of our experts.

    4. We prefer the PMU for core benchmarking.

    5, 6, 7.  I will ask one of our experts.