LM4F SSI never stop sending out data even if i stop putting data to the SSI TX FIFO

Hi,

Some major problems:

1. a) Your code contradicts your declared intent - your wish is to send a word 30 times, but you never count these x times. Shouldn't that be counted?
2. b) You keep secret the value of SPI_FPGA_BITRATE - maybe SPI_FPGA_BITRATE * 16 * 30 to be less or equal than 200 ms? hard to know.
3. c) You want to have a periodic process, which is good - so that's why you have a waveform on oscilloscope - if this correspond or not to your intent is hard to guess due to previous point. The waveform may be good or not, but is normal to have it due to calls: TimerInthandler->SPIFPGASSendDataPtr()->SSIDataPutNonBlocking().
4. d) Not a good idea to use UART sending within other interrupts. Keep that outside timer interrupt - use your UART interrupt or just send a flag to main to process that.
5. e) Not a good idea to have a blank while(1) loop - if your program(s) grow, it may lead you to subtle bugs, hard to discover. While TI uses that as demo in some examples is OK, but look for some serious  examples and that is not anymore the case.

Petrei

Hi Petrei,

First of all, thanks for your reply.

This is a test program for test the communication between LM4F and FPGA. So the coding isn't good.

For the first problem:

1.  

static int timesss = 30;

SPIFPGASSSendDataptr(unsigned short *senddata, short datalength)

{

    unsigned long ulData;

    if (timesss-- > 0)

    {

      ulData = (unsigned long)(senddata[0]);

     //Just use Uart to send debug message to indicate that transfer data to SSI has finished

      memset(aa,0,50);

      sprintf(aa,"R:%d\r\n",success);

      SendDataToUart((unsigned char *)aa, 50);

      return SSIDataPutNonBlocking(SSI1_BASE, ulData);

}

For the second:

SPI_FPGA_BITRATE is 3.125M, so it is large enough.

But would you please tell me why should multiply 16 and 30?

For the third one:

The waveform is ok on oscilloscope if i continue sending data through SPI, but from above code, i send the data 30 times, so there should be no data sending out after 30 times.

For the forth one:

It is only for debugging, i will remove it in formal version

For the fifth one:

I will add something like a sleep in while 1

But i still don't understand why there is data sending out through TX after running for 30 times.

Do you have any more suggestion for this?

Thanks

Hi,

For 1) - sorry - i missed timesss...

For 2) - SPI_FPGA_BITRATE - I meant the period for that * 16 * 30 will give you the whole package duration, which should be less than 200 ms; but you confirm is OK?

I suggest you to set the master mode for test and see if the problem persist .

Petrei

Thanks again for you reply.

I will try out the master mode tomorrow.

As it is Midnight here in China.

I will let you know the result, Thanks again.

@Petrei - Pardon - perhaps this simply "builds" upon your great assistance - but I suspect may be helpful...

Followed this w/interest - when logic seemingly fails - time to reach for dreaded, "Errata" (Oct 17, 2012) ...  And the following reveals:

You appear "snake-bit" in two areas:  First one - we can overcome... dial down from 80 to 50MHz (we confirm that works)

change: SYSCTL_SYSDIV_2_5  to   SYSCTL_SYSDIV_4  to comply w/errata

and:  Alas you are using the exact SSI Mode - below flagged/described!   (bloody rotten - your luck) 

Appears you can overcome by operating the SSI clock at greater than 1.1MHz

Again - poster Petrei has done the "heavy lifting" - hope this brief report helps resolve...

Also, to the original stated issue - the SSI continues to transmit even when you don't feed it data - this will always be the case in slave mode.  Since the SSI clocking is driven externally by the master, it has no choice but to send data whenever the master drives the clock, even if you haven't prepared any data to send.  If you stop feeding the FIFO, the data that's sent is not defined - but most probably will be either the last value you wrote to the FIFO send repeatedly, or it will cycle through the contents of the FIFO repeatedly.

slandrum said:

SSI continues to transmit even when you don't feed it data - this will always be the case in slave mode.

This is most excellent, vital commentary - imho - thank you Slandrum.

Unsaid throughout is the behavior of the Master - and how this may be "originator/source" of this issue.

This said - complying w/any/all Errata restrictions, or dictates (as past posted) should be first order of business...

Hi,

@cb1_mobile and @slandrum - thanks for the info, I completely ignored the errata sheet ...

Petrei

@Petrei - as did we all - dragged kicking/screaming when little else makes sense...

Hi slandrum,

Thanks for your reply.

Really help me a lot.

Do you have any idea on how to solve this problem?

Do i have to appy SSIDataPut(SSI1_BASE, 0x00) eight times (as the depth of TX FIFO is 8 deep) each time i finished sending data to the SPI master side?

I want the TX port of SSI to be 0x00 each time after sending data, but not the last data i send.

Do you have any suggestion about this? 

Thanks in advance.

Perhaps unwise to fully dismiss (searched/discovered/gold-plate presented) Errata.  (this reporter exits...)

Hi All,

I have found how to slove the problem, use DMA mode to send the SPI data.

If you are operating the MCU in desregard of published errata - one may "think twice" about "long-term" health of your device.  One device may "squeak by" errata guard-band - but multiple likely will not...