LM4F232H5QD: differential ADC problem

Hi Shriram,

    Please check the revision of the LM4F232 that you are using, and then take a look at the errata for the ADC: http://www.ti.com/lit/er/spmz636d/spmz636d.pdf

    The Revision is on the microcontroller part markings, third row, last two digits.  I have an LM4F232 eval board with the Rev. A1 part, so the ADC errata would affect my board.  You probably have Rev. A0 or Rev. A1 of the LM4F232. 

    Best,

      Rick Nardone 

Hi Rick,

Appreciate your help.

I've checked Rev No of LM4F232H5QD placed on my board. Its 'A1'. Therefore after referring to the errata, I noticed that additional settings needs to be done for proper functioning of external reference voltage (Section 11.1 'External reference requires additional configuration'). I have configured this setting but it didn't solve problem.

I added one line in code to set the PB6 BIT as 'HWREG(GPIO_PORTB_BASE + GPIO_O_AMSEL) |= GPIO_PIN_6;'

Regards,

Shriram

HI Shriram,

Check to see if you have the StepConfigure correct.  I think you need to ad the ADC_CTL_END to tell the sequencer you are at the end of the sequence.

Your code:

ADCSequenceStepConfigure(ADC1_BASE, SQNC_NUM_0, 0, ADC_CTL_D | ADC_CTL_CH2);

Thanks,

    Rick

Good Morning Rick,

Thanks for suggestion but I have tried this combination and  problem still persist.

However, I was able to make it functional in differential mode in another fashion. Now I've reconfigured differential ADC using following settings - 

1. 1msec Timer A used for triggering ADC (earlier, it was processor based trigger)

2. Wrote ADC1_Sequence0_ISR in which cleared ADC interrupt, and read ADC data (earlier it was polling for raw interrupt status).

Now my Initialization sequence of ADC looks like this:

{

    SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_ADC1)){;}

    ADCSequenceConfigure(ADC1_BASE, SQNC_NUM_0, ADC_TRIGGER_TIMER, 0);
    ADCSequenceStepConfigure(ADC1_BASE, SQNC_NUM_0, 0, ADC_CTL_IE | ADC_CTL_END | ADC_CTL_D | ADC_CTL_CH0);
    ADCReferenceSet(ADC1_BASE, ADC_REF_EXT_3V); //errata
    HWREG(GPIO_PORTB_BASE + GPIO_O_AMSEL) |= GPIO_PIN_6;
    ADCSequenceEnable(ADC1_BASE, SQNC_NUM_0);
    ADCIntRegister(ADC1_BASE, SQNC_NUM_0, ISR_ADC1_Seqnc0);
    ADCIntEnable(ADC1_BASE, SQNC_NUM_0);
    TimerControlTrigger(TIMER0_BASE, TIMER_A, true);

} //end of ADC init

ISR looks like:

{

    ADCIntClear(ADC1_BASE, SQNC_NUM_0);
    GPIO_PORTG_DATA_R ^= GPIO_PIN_2;
    slSampleCopied = ADCSequenceDataGet(ADC1_BASE, SQNC_NUM_0, &ulADC1_Count);

} //end of ISR

Now ADC is working in differential mode but concern still remains, why with processor based trigger and polling mechanism, it is not working.

Now you have both kind of codes, would you be able to conclude ?

Regards,

Shriram

Hi Shriram,

There is an exellent example of using the ADC in polled mode in the Stellaris Lanchpad Workshop: http://processors.wiki.ti.com/index.php/Getting_Started_with_the_Stellaris_EK-LM4F120XL_LaunchPad_Workshop?DCMP=Stellaris&HQS=StellarisLaunchPadWorkshop

Take a look at the way this example clears the interrupt in polled mode. 

Best,

    Rick