Access Time

Pierre,

A LDR or STR instruction onchip RAM takes 3 CPU cycles to complete.

Thanks and regards,

Zhaohong

Pashan,

It is true for all TI devices based on Cortex R4. Cortex R4 tries to improve the accessing time by speculative fetch. If the data is already fetched into CPU buffer when LDR executes, it becomes a one cycle instruction.

Thanks and regards,

Zhaohong

Hello Zhahong,

In the following link :

http://www.arm.com/files/pdf/Cortex-R4-white-paper.pdf

 I see that typical value is 2 cycles instead of 3 cycles as mentioned by you. Please confirm if ARM document is wrong.

I am assuming ATCM [Flash] and BTCM [RAM], both have 3 Cycles of Access Time as mentioned by you.

Thank you.

Regards

Pashan

Maybe "typical access time" = "average"... and average(3cyles normal mode,1cycle when fetched)=2cycles ?
It's so marketing!