To Haixiao - TMS570LS3137 MIBSPI and DMA configuration issue

Haixiao,

Thanks for the quick answer.

Have a good weekend!

Yanzhong

Haixiao,

This is Huichun, Yanzhong's workmate. Yanzhong is off this week, my question is for the SPI configuration(one master, one slave), we can get the the ADC data acquisition of two channels simutanuously. Both two channels use DMA, so can the DMA supports two channels(SPI) simutanuously? or there is a little latency of one from the other due to shared peripheral bus if there is?  Thanks,

huichun

Yes, there will be a little big latency since this chip only has one DMA master. But this latency is tiny. DMA is running at the HCLK frequency, e.g180MHz, it access the peripheral bus faster (same frequency as the CPU but less latency than the CPU) than the R4F CPU. Use the DMA if possible.

Regards,

Haixiao

Hi, Haixiao, It's me. It's not easy to find you in the world. Fortunately the internet is powerful.

Happy birthday!

Fengrong

(fengrong.ji@clariant.com)

Haixiao,

I did some tests for Huichun's concern about the DMA latency between the two SPI channels.

You are right. The latency can be ignored. 

But I do need your advice for configure the settings in a right way -

I use IAR Embedded Workbench IDE.  Every time I started the debugger by loading the program into Flash and executing it, I got the correct two channel data without latency. ( I set the board to read 1000 sets of data. Both channels started to get data from the 2nd reading.)

When I clicked the debugger "reset" button (it supposes the debugger generate a reset signal to MCU) and executed the program, the two channels cannot read the data simulatanuously. For example, one channel (SPI Master) started to get data from the 33rd reading, the other (SPI Slave) started to get data from the 26th reading (the data is associated to the 33rd at the 1st channel). The latency between the two channel readings can be repeated unless I change the trigger signal frequency (I use a continuous squaredwave signal to trigger MIBSPI TG). 

This might be related to my initialization - I may need to clear all the related flags/status bits before start to enable MIBSPI and DMA.

Hope to hear your analysis and the solution. (what need to be cleared?)

Note that my system is using SPI-1 (Master, MibSPI mode) and SPI-3 (Slave MibSPI mode), and DMA. The initialization code was attached before.

Thanks,

Yanzhong 

What does 2nd /33rd reading mean?

What is your concern?

Thanks for your post. See, your post served as the facebook and helped my highschool classmate find me.

Regards,

Haixiao

Haixiao,

It's always great finding an old friend. Congritulations! - You became popular so easy when you work as an expert in the forum :-)

1) The 26th/33rd readings are the data pointer # in my data array that the two DMA channels transfer and store data in the RAM.

For example, in the case of the code was loaded into flash and started 1st execution (it just has the system initializations and a non-operation forever "while" loop),    MIBSPI1 TG0 and MIBSPI3 TG0 were triggered by the external trigger pulses at GIOA-pin2. Then the MIBSPI data were taken by DMA and stored in data array AI_A[*] and AI_B[*] respectively. For each trigger event, one set of data (dual channel)  were read, transfered, and stored .

The DMA was set as one element per frame, frame trigger.  The frame count is 1000. i.e. the data array is from AI_A[0] to AI_A[999].

AI_A[0] = 0x0000   AI_B[0]=0x0000   - both channels missed the first trigger data, it's ok.

AI_A[1] = 0x055E   AI_B[1]=0x0560  - from the 2nd trigger, both channels got the same data  (both ADCs have the same Analog Input signal)

AI_A[2] = 0x052A   AI_B[2]=0x052C

AI_A[3] = 0x04F4   AI_B[3]=0x04F6

:

:

AI_A[999] = 0x0360   AI_B[999]=0x0362 - the last set of the 1000 data

2) based on above, when I clicked the "reset" botton in the IAR IDE debugger, the program pointer was reset to the start point, then I re-run the same code. 

See the data array I got as below

AI_A[0] = 0x0000   AI_B[0]=0x0000   - both channels missed the data

AI_A[1] = 0x0000   AI_B[1]=0x0000  -

:

AI_A[25] = 0x0000   AI_B[25]=0x0000

AI_A[26] = 0x0000   AI_B[26]=0x068C  - from the 26th trigger, channel-B (slave SPI) started to get data and saved

AI_A[27] = 0x0000   AI_B[27]=0x06A1

AI_A[28] = 0x0000   AI_B[28]=0x0679

AI_A[29] = 0x0000   AI_B[29]=0x0654

AI_A[30] = 0x0000   AI_B[30]=0x062B

AI_A[31] = 0x0000   AI_B[31]=0x0601

AI_A[32] = 0x0000   AI_B[32]=0x05D3

AI_A[33] = 0x068B   AI_B[33]=0x05A3  - from the 33rd trigger, channel-A (master SPI) started to get data and stored. the AI_A[33] value matches AI_B[26]

AI_A[34] = 0x069F   AI_B[34]=0x0571  - the AI_A[34] value matches AI_B[27]

AI_A[35] = 0x0677   AI_B[35]=0x053D - the AI_A[35] value matches AI_B[28]

AI_A[36] = 0x0652   AI_B[36]=0x0508 - the AI_A[36] value matches AI_B[29]

Based on the data above, compare to the case of 1st code execution, there were two phenomena observed:

(1) Both channels were delayed to get the 1st data.  the start point 26th/33rd can be repeated if remains the trigger signal frequency unchanged.

(2) Channel-A started to get data ran a few trigger events late - (there still were same data value) 

The data reading start point and the delay of trigger events # will change if the trigger signal frequency is changed.

I am thinking this might be caused by the incomplete initialization.  After the 1st execution, some status were remained even if the MCU was reset, and they affected the following MibSPI or DMA operations.

I'd like to get your advice before I start to try different settings.

Yanzhong

Sounds timing problems to me. Do you mean:

SPI1 CLK and CS drives both SPI3 and the AD chip?

SPI1 SIMO - AD chip chan1 -SDI

SP1 SOMI - AD chip chan1-SDO

SPI3 SIMO - AD chip chan2 -SDO

SP13SOMI - AD chip chan2-SDI

If this is true, there are timing problems.

The AD chip does not have SDI signals. So, SPI1 SIMO and SPI3 SOMI were not connected.

The SPI1 write a dummy to generate /CS and SPI clock to SPI3 and AD chip. The AD chip use these clocks to provide two channel data to SPI1 SIMO and SPI3 SOMI simultaneously.

I did not see any timing issue.  and the "1st time" data reading (i.e. in debugger, after the flash programed), I can get the right data at both channels.

Please explain what are the timing problems you concerned.

Thanks,

Yanzhong

Can you set the slave SPI3 as "trigger always"? Just want to make sure that SPI3 have enough time to prepare the data response to the SPI1 transfer.

I don't understand why you get zeros in the DMA data. 2 possiblities:

1) AD chip send zero value through SPI when the GIO trigger occurs (can you look at the data through a oscilliscope or logic analyzer?)

2) SPI did not receive the data correctly. (Can you slow down the GIO trigger to catch such receive mismatch point and check the SPI RAM?)

3) DMA did not handle the data correct.

Regards,

Haixiao