I am running into a problem when I am trying to turn on an interrupt to capture floating point exceptions. I have some initial thoughts on some work-arounds for the issue, but wanted to get some suggestions as I don't like the work-arounds I am coming up with. Here is the scenario:
I have turned on the VIM reporting of the Divide By Zero floating point exception via the appropriate bit in the ARM Secondary Auxiliary Control Register. I have also enabled the VIM interrupt and provided my interrupt function (currently written in C code). I then force a floating point divide by zero, and I am entering my ISR as expected. My understanding is that I need to manually write a "0" back to the DZC bit (Division by Zero cumulative flag) in the FPSCR register in order to clear this bit and subsequently clear the VIM interrupt request flag. The problem is that the FPSCR register is saved and restored by the compiler when I enter/leave this ISR (which I think makes sense given that the FPSCR also holds the N,Z,C,V flags). This is basically making it impossible to leave the ISR without restoring the DZC bit to 1 (as this being 1 was what got me into the ISR to begin with) and subsequently triggering another VFP VIM interrupt.
Any thoughts on if my understanding is incorrect on any of this? Any workarounds that can be suggested? I didn't necessarily want to have to write the ISR completely in assembly language to put custom code on the restoration of the FPSCR register.
Thanks,
Luke